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CYF0072V18L-133BGXI Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CYF0072V18L-133BGXI Datasheet(HTML) 9 Page - Cypress Semiconductor |
9 / 29 page CYF0018V, CYF0036V CYF0072V Document Number: 001-53687 Rev. *H Page 9 of 29 Table 2. Configuration Registers ADDR Configuration Register Default Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] Bit [0] 0x1 Reserved 0x00 X X X X X X X X 0x2 Reserved 0x00 X X X X X X X X 0x3 Reserved 0x00 X X X X X X X X 0x4 Almost-Empty Flag generation address - (LSB) (N) 0x7F D7 D6 D5 D4 D3 D2 D1 D0 0x5 Almost-Empty Flag generation address - (MSB) (N) 0x00 XX X X XX D9 D8 0x6 Reserved 0x00 X X X X X X X X 0x7 Almost-Full Flag generation address - (LSB) (M) 0x7F D7 D6 D5 D4 D3 D2 D1 D0 0x8 Almost-Full Flag generation address - (MSB) (M) 0x00 XX X X XX D9 D8 0x9 Reserved 0x00 X X X X X X X X 0xA Fast CLK Bit Register 1XXXXXXXb Fast CLK bit XX X X X X X Table 3. Writing and Reading Configuration Registers in Parallel Mode SPI_SEN LD WEN REN WCLK RCLK SPI_SCLK Operation 10 0 1 First rising edge because both LD and REN are low X X Parallel write to first register 10 0 1 Second rising edge X X Parallel write to second register 10 0 1 Third rising edge X X Parallel write to third register 10 0 1 Fourth rising edge X X Parallel write to fourth register 10 0 1 XX 10 0 1 XX 10 0 1 XX 10 0 1 Tenth rising edge X X Parallel write to tenth register 10 0 1 Eleventh rising edge X X Parallel write to first register (roll back) 10 1 0 X First rising edge since both LD and REN are low X Parallel read from first register 10 1 0 X Second rising edge X Parallel read from second register 10 1 0 X Third rising edge X Parallel read from third register 10 1 0 X Fourth rising edge X Parallel read from fourth register 10 1 0 X X 10 1 0 X X 10 1 0 X X 10 1 0 X Tenth rising edge X Parallel read from tenth register |
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