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STK12C68 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part No. STK12C68
Description  64 Kbit (8K x 8) AutoStore nvSRAM 25 ns, 35 ns, and 45 ns access times
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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STK12C68 Datasheet(HTML) 3 Page - Cypress Semiconductor

 
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STK12C68
Document Number: 001-51027 Rev. *C
Page 3 of 24
Pin Configurations
Pin Definitions
Pin Name
Alt
I/O Type
Description
A0–A12
Input
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
DQ0-DQ7
Input or Output Bidirectional Data I/O Lines. Used as input or output lines depending on operation.
WE
W
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O
pins is written to the specific address location.
CE
E
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
G
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
VSS
Ground
Ground for the Device. The device is connected to ground of the system.
VCC
Power Supply Power Supply Inputs to the Device.
HSB
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
VCAP
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
Figure 1. 28-Pin SOIC/DIP and LLC
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