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STK12C68 Datasheet(PDF) 15 Page - Cypress Semiconductor

Part No. STK12C68
Description  64 Kbit (8K x 8) AutoStore nvSRAM 25 ns, 35 ns, and 45 ns access times
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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STK12C68 Datasheet(HTML) 15 Page - Cypress Semiconductor

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STK12C68
Document Number: 001-51027 Rev. *C
Page 15 of 24
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [18]
Parameter
Alt
Description
25 ns
35 ns
45 ns
Unit
Min
Max
Min
Max
Min
Max
tRC[14]
tAVAV
STORE/RECALL Initiation Cycle Time
25
35
45
ns
tSA[17]
tAVEL
Address Setup Time
0
0
0
ns
tCW[17]
tELEH
Clock Pulse Width
20
25
30
ns
tHACE[17]
tELAX
Address Hold Time
20
20
20
ns
tRECALL
RECALL Duration
20
20
20
μs
Switching Waveform
Figure 12. CE Controlled Software STORE/RECALL Cycle [18]
tRC
tRC
tSA
tSCE
tHACE
tSTORE / tRECALL
DATA VALID
DATA VALID
6
#
S
S
E
R
D
D
A
1
#
S
S
E
R
D
D
A
HIGH IMPEDANCE
ADDRESS
CE
OE
DQ (DATA)
Notes
17. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
18. The six consecutive addresses must be read in the order listed in Table 1 on page 7. WE must be HIGH during all six consecutive cycles.
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