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CYD02S36VA-167BBC Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CYD02S36VA-167BBC Datasheet(HTML) 10 Page - Cypress Semiconductor |
10 / 28 page CYD02S36V/36VA Document Number: 38-06076 Rev. *J Page 10 of 28 IEEE 1149.1 Serial Boundary Scan (JTAG)[18] The FLEx36 family devices incorporate an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1-compliant TAPs. The TAP operates using JEDEC-standard 3.3V IO logic levels. It is composed of three input connections and one output connection required by the test logic defined by the standard. Performing a TAP Reset A reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This reset does not affect the operation of the devices, and may be performed while the device is operating. An MRST must be performed on the devices after power up. Performing a Pause/Restart When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan chain outputs the next bit in the chain twice. For example, if the value expected from the chain is 1010101, the device outputs a 11010101. This extra bit causes some testers to report an erroneous failure for the devices in a scan test. Therefore the tester must be configured to never enter the PAUSE-DR state. 215 214 26 21 25 22 24 23 20 215 214 26 21 25 22 24 23 20 215 214 26 21 25 22 24 23 20 215 214 26 21 25 22 24 23 20 H H L H 11 0s 1 0 1 0 1 01 00 Xs 1 X 0 X 0 X0 11 Xs 1 X 1 X 1 X1 00 Xs 1 X 0 X 0 X0 Masked Address Unmasked Address Mask Register bit-0 Address Counter bit-0 CNTINT Example: Load Counter-Mask Register = 3F Load Address Counter = 8 Max Address Register Max + 1 Address Register Figure 3. Programmable Counter-Mask Register Operation[17] Table 4. Identification Register Definitions Instruction Field Value Description Revision number (31:28) 0h Reserved for version number. Cypress device ID (27:12) C001h Defines Cypress part number for CYD02S36V/36VA Cypress JEDEC ID (11:1) 034h Allows unique identification of the DP family device vendor. ID register presence (0) 1 Indicates the presence of an ID register. Notes 17. The “X” in this diagram represents the counter upper bits. 18. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance. [+] Feedback |
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