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CY62128EV30LL-45ZAXI Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY62128EV30LL-45ZAXI Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 15 page  CY62128EV30 MoBL® 1-Mbit (128 K × 8) Static RAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-05579 Rev. *I Revised January 6, 2011 1-Mbit (128 K × 8) Static RAM Features ■ Very high speed: 45 ns ■ Temperature ranges: ❐ Industrial: –40 °C to +85 °C ■ Wide voltage range: 2.2 V to 3.6 V ■ Pin compatible with CY62128DV30 ■ Ultra low standby power ❐ Typical standby current: 1 µA ❐ Maximum standby current: 4 µA ■ Ultra low active power ❐ Typical active current: 1.3 mA at f = 1 MHz ■ Easy memory expansion with CE1, CE2, and OE features ■ Automatic power-down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Offered in Pb-free 32-pin SOIC, 32-pin thin small outline package (TSOP) I, and 32-pin shrunk thin small outline package (STSOP) packages Functional Description The CY62128EV30[1] is a high performance CMOS static RAM module organized as 128 K words by 8-bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. Placing the device in standby mode reduces power consumption by more than 99 percent when deselected (CE1 HIGH or CE2 LOW). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). To write to the device, take chip enable (CE1 LOW and CE2 HIGH) and write enable (WE) inputs LOW. Data on the eight I/O pins is then written into the location specified on the address pin (A0 through A16). To read from the device, take chip enable (CE1 LOW and CE2 HIGH) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. A0 I/O0 I/O7 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 A1 A2 A3 A4 A5 A6 A7 A8 A9 POWER DOWN WE OE COLUMN DECODER 128K x 8 ARRAY INPUT BUFFER A10 A11 CE1 CE2 Logic Block Diagram Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com. [+] Feedback |
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