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CY24130ZXC-1T Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY24130ZXC-1T Datasheet(HTML) 1 Page - Cypress Semiconductor |
1 / 6 page CY24130 HOTLink II™ SMPTE Receiver Training Clock Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-07711 Rev. *A Revised May 22, 2008 Features ■ Integrated phase-locked loop ■ Low-jitter, high-accuracy outputs ■ 3.3V operation Benefits ■ Internal PLL with up to 400-MHz internal operation ■ Meets critical timing requirements in complex system designs ■ Enables application compatibility Table 1. Frequency table Part Number Outputs Input Frequency Output Frequency Range CY24130-1 2 27 MHz (Driven Reference) 1 copy 27-MHz reference clock output 1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable) CY24130-2 2 27 MHz (Crystal Reference) 1 copy 27-MHz reference clock output 1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable) XIN XOUT OUTPUT MULTIPLEXER AND DIVIDERS PLL OSC. CLKA Q P VCO VDDL AVSS Φ AVDD VSS S0 S1 REFCLK S2 VDD VSSL Logic Block Diagram Table 2. Frequency Select Options S2 S1 S0 CLKA REFCLK Units 0 0 0 27 27 MHz 0 0 1 36 27 MHz 0 1 0 54 27 MHz 0 1 1 148.50 27 MHz 100 74.25 27 MHz 1 0 1 OFF, pulled low 27 MHz 1 1 0 OFF, pulled low 27 MHz 1 1 1 OFF, pulled low 27 MHz [+] Feedback |
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