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CY8C21645 Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY8C21645
Description  Automotive PSoC짰 Programmable System-on-Chip?
Download  36 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C21645 Datasheet(HTML) 8 Page - Cypress Semiconductor

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CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
Document Number: 001-55397 Rev. *I
Page 8 of 36
Pinouts
The automotive CY8C21x45 and CY8C22x45 PSoC devices are available in a variety of packages which are listed and illustrated in
the following tables. Every port pin (labeled with a “P”) is capable of digital I/O and connection to the common analog mux bus.
However, VSS, VDD, and XRES are not capable of digital I/O.
28-Pin Part Pinout
Table 2. 28-Pin Part Pinout (SSOP)
Pin
No.
Type
Pin Name
Description
Digital
Analog
Figure 3. CY8C21345, CY8C22345, and CY8C22345H
28-Pin PSoC Device
1
I/O
I, MR
P0[7]
Analog column mux input, CMOD
capacitor pin
2
I/O
I, ML
P0[5]
Analog column mux input, CMOD
capacitor pin
3
I/O
I, ML
P0[3]
Analog column mux input
4
I/O
I, ML
P0[1]
Analog column mux input
5
I/O
I, ML
P2[7]
Direct input to analog block
6
I/O
ML
P2[5]
Optional SAR ADC external reference
(EXTREF)
7
I/O
ML
P2[3]
8
I/O
ML
P2[1]
9
Power
VSS
Ground connection
10
I/O
ML
P1[7]
I2C Serial Clock (SCL)
11
I/O
ML
P1[5]
I2C Serial Data (SDA)
12
I/O
ML
P1[3]
13
I/O
ML
P1[1]
Crystal Input (XTALin), I2C SCL,
ISSP-SCLK[5]
14
Power
VSS
Ground Connection
15
I/O
MR
P1[0]
Crystal Output (XTALout), I2C SDA,
ISSP-SDATA[5]
16
I/O
MR
P1[2]
17
I/O
MR
P1[4]
Optional external clock input (EXTCLK)
18
I/O
MR
P1[6]
19
Input
XRES
Active high external reset with internal
pull-down
20
I/O
MR
P2[0]
21
I/O
MR
P2[2]
22
I/O
MR
P2[4]
23
I/O
I, MR
P2[6]
Direct input to analog block
24
I/O
I, MR
P0[0]
Analog column mux input
25
I/O
I, MR
P0[2]
Analog column mux input
26
I/O
I, MR
P0[4]
Analog column mux input
27
I/O
I, MR
P0[6]
Analog column mux input
28
Power
VDD
Supply voltage
LEGEND: A = Analog, I = Input, O = Output, MR= Right analog mux bus input, ML= Left analog mux bus input.
SSOP
1
AI, MR, P0[7]
AI, ML, P0[5]
AI, ML, P0[3]
AI, ML, P0[1]
AI, ML, P2[7]
EXTREF, ML, P2[5]
ML, P2[3]
ML, P2[1]
VSS
I2C SCL, ML, P1[7]
I2C SDA, ML, P1[5]
ML, P1[3]
XTALin, I2C SCL, ML, P1[1]
VSS
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
P0[6], MR, AI
P0[4], MR, AI
P0[2], MR, AI
P0[0], MR, AI
P2[6], MR, AI
P2[4], MR
P2[2], MR
P2[0], MR
XRES
P1[6], MR
P1[4], MR, EXTCLK
P1[2], MR
P1[0], MR, I2C SDA, XTALout
Note
5. These are the ISSP pins, which are not High Z after exiting a reset state. See the PSoC Technical Reference Manual for CY8C21x45 and CY8C22x45 devices for details.
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