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CY8C3665AXI-017 Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY8C3665AXI-017 Datasheet(HTML) 5 Page - Cypress Semiconductor |
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5 / 125 page  PSoC® 3: CY8C36 Family Data Sheet Document Number: 001-53413 Rev. *K Page 5 of 125 The CY8C36 family supports a wide supply operating range from 1.71 to 5.5 V. This allows operation from regulated supplies such as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or directly from a wide range of battery types. In addition, it provides an integrated high efficiency synchronous boost converter that can power the device from supply voltages as low as 0.5 V. This enables the device to be powered directly from a single battery or solar cell. In addition, you can use the boost converter to generate other voltages required by the device, such as a 3.3-V supply for LCD glass drive. The boost’s output is available on the VBOOST pin, allowing other devices in the application to be powered from the PSoC. PSoC supports a wide range of low-power modes. These include a 200-nA hibernate mode with RAM retention and a 1-µA sleep mode with RTC. In the second mode the optional 32.768-kHz watch crystal runs continuously and maintains an accurate RTC. Power to all major functional blocks, including the programmable digital and analog peripherals, can be controlled independently by firmware. This allows low-power background processing when some peripherals are not in use. This, in turn, provides a total device current of only 1.2 mA when the CPU is running at 6 MHz, or 0.8 mA running at 3 MHz. The details of the PSoC power modes are covered in the “Power System” section on page 28 of this data sheet. PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for programming, debug, and test. The 1-wire SWV may also be used for ‘printf’ style debugging. By combining SWD and SWV, you can implement a full debugging interface with just three pins. Using these standard interfaces enables you to debug or program the PSoC with a variety of hardware solutions from Cypress or third party vendors. PSoC supports on-chip break points and 4-KB instruction and data race memory for debug. Details of the programming, test, and debugging interfaces are discussed in the “Programming, Debug Interfaces, Resources” section on page 59 of this data sheet. 2. Pinouts The Vddio pin that supplies a particular set of pins is indicated by the black lines drawn on the pinout diagrams in Figure 2-1 through Figure 2-4. Using the Vddio pins, a single PSoC can support multiple interface voltage levels, eliminating the need for off-chip level shifters. Each Vddio may sink up to 100 mA total to its associated I/O pins and opamps. On the 68-pin and 100-pin devices each set of Vddio associated pins may sink up to 100 mA. The 48-pin device may sink up to 100 mA total for all Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all Vddio1 plus Vddio3 associated I/O pins. Figure 2-1. 48-pin SSOP Part Pinout Notes 4. This feature on select devices only. See Ordering Information on page 112 for details. 5. GPIOs with opamp outputs are not recommended for use with CapSense. SSOP Vssa (SIO) P12[3] 247 Vcca (OpAmp2out, GPIO) P0[0] 346 P15[3] (GPIO, kHz XTAL: Xi) (OpAmp0out, GPIO) P0[1] 445 P12[0] (SIO, I2C1: SCL) Vddio0 742 P12[1] (SIO, I2C1: SDA) 643 (OpAmp0-/Extref0, GPIO) P0[3] P15[1] (GPIO, MHz XTAL: Xi) (OpAmp2-, GPIO) P0[5] 940 P15[0] (GPIO, MHz XTAL: Xo) (IDAC0, GPIO) P0[6] 10 39 Vccd (IDAC2, GPIO) P0[7] 11 38 Vssd Vccd 12 37 Vddd Vssd 13 36 P15[7] (USBIO, D-, SWDCK) Vddd 14 35 P15[6] (USBIO, D+, SWDIO) (GPIO) P2[3] 15 34 P1[7] (GPIO) (GPIO) P2[4] 16 33 P1[6] (GPIO) Vddio2 17 32 Vddio1 (GPIO) P2[5] 18 31 P1[5] (GPIO, nTRST) (GPIO) P2[6] 19 30 P1[4] (GPIO, TDI) (GPIO) P2[7] 20 29 P1[3] (GPIO, TDO, SWV) Vssb 21 28 Ind 22 27 P1[1] (GPIO, TCK, SWDCK) Vboost 23 26 P1[0] (GPIO, TMS, SWDIO) Vbat 24 25 Vdda (SIO) P12[2] 148 Vddio3 (OpAmp2+, GPIO) P0[4] 841 P15[2] (GPIO, kHz XTAL: Xo) (OpAmp0+, GPIO) P0[2] 544 Lines show Vddio to I/O supply association P1[2] (GPIO, configurable XRES) [6] [6] [+] Feedback |
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