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K4B4G0846B-MCF7 Datasheet(PDF) 11 Page - Samsung semiconductor |
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K4B4G0846B-MCF7 Datasheet(HTML) 11 Page - Samsung semiconductor |
11 / 59 page Page 11 of 59 Rev. 1.0 March 2009 DDP 4Gb DDR3 SDRAM K4B4G0446B K4B4G0846B 5.0 DDR3 SDRAM Addressing 1Gb Configuration 256Mb x 4 128Mb x 8 64Mb x 16 # of Bank 8 8 8 Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2 Auto precharge A10/AP A10/AP A10/AP Row Address A0 - A13 A0 - A13 A0 - A12 Column Address A0 - A9,A11 A0 - A9 A0 - A9 BC switch on the fly A12/BC A12/BC A12/BC Page size *1 1 KB 1 KB 2 KB Note 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG ÷8 where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits 2Gb Configuration 512Mb x 4 256Mb x 8 128Mb x 16 # of Bank 8 8 8 Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2 Auto precharge A10/AP A10/AP A10/AP Row Address A0 - A14 A0 - A14 A0 - A13 Column Address A0 - A9,A11 A0 - A9 A0 - A9 BC switch on the fly A12/BC A12/BC A12/BC Page size *1 1 KB 1 KB 2 KB 4Gb Configuration 1Gb x 4 512Mb x 8 256Mb x 16 # of Bank 8 8 8 Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2 Auto precharge A10/AP A10/AP A10/AP Row Address A0 - A15 A0 - A15 A0 - A14 Column Address A0 - A9,A11 A0 - A9 A0 - A9 BC switch on the fly A12/BC A12/BC A12/BC Page size *1 1 KB 1 KB 2 KB 8Gb Configuration 2Gb x 4 1Gb x 8 512Mb x 16 # of Bank 8 8 8 Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2 Auto precharge A10/AP A10/AP A10/AP Row Address A0 - A15 A0 - A15 A0 - A15 Column Address A0 - A9,A11,A13 A0 - A9,A11 A0 - A9 BC switch on the fly A12/BC A12/BC A12/BC Page size *1 2 KB 2 KB 2 KB |
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