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CY7C1429KV18 Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CY7C1429KV18 Datasheet(HTML) 7 Page - Cypress Semiconductor |
7 / 32 page CY7C1422KV18, CY7C1429KV18 CY7C1423KV18, CY7C1424KV18 Document Number: 001-57829 Rev. *B Page 7 of 32 Pin Definitions Pin Name I/O Pin Description D[x:0] Input- synchronous Data input signals. Sampled on the rising edge of K and K clocks during valid write operations. CY7C1422KV18 - D[7:0] CY7C1429KV18 - D[8:0] CY7C1423KV18 - D[17:0] CY7C1424KV18 - D[35:0] LD Input- synchronous Synchronous load. This input is brought LOW when a bus cycle sequence is defined. This definition includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period of bus activity). NWS0, NWS1 Nibble write select 0, 1 active LOW (CY7C1422KV18 only). Sampled on the rising edge of the K and K clocks during Write operations. Used to select which nibble is written into the device during the current portion of the Write operations. Nibbles not written remain unaltered. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All nibble write selects are sampled on the same edge as the data. Deselecting a nibble write select ignores the corresponding nibble of data and it is not written into the device. BWS0, BWS1, BWS2, BWS3 Input- synchronous Byte write select 0, 1, 2, and 3 active LOW. Sampled on the rising edge of the K and K clocks during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1429KV18 BWS0 controls D[8:0] CY7C1423KV18 BWS0 controls D[8:0], BWS1 controls D[17:9]. CY7C1424KV18 BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select ignores the corresponding byte of data and it is not written into the device. A Input- synchronous Address inputs. Sampled on the rising edge of the K clock during active read and write operations. These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 4 M × 8 (2 arrays each of 2 M × 8) for CY7C1422KV18, 4 M × 9 (2 arrays each of 2 M × 9) for CY7C1429KV18, 2 M × 18 (2 arrays each of 1 M × 18) for CY7C1423KV18 and 1 M × 36 (2 arrays each of 512 K × 36) for CY7C1424KV18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1422KV18 and CY7C1429KV18, 20 address inputs for CY7C1423KV18 and 19 address inputs for CY7C1424KV18. These inputs are ignored when the appropriate port is deselected. Q[x:0] Outputs- synchronous Data output signals. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the C and C clocks during read operations, or K and K when in single clock mode. When the read port is deselected, Q[x:0] are automatically tristated. CY7C1422KV18 Q[7:0] CY7C1429KV18 Q[8:0] CY7C1423KV18 Q[17:0] CY7C1424KV18 Q[35:0] R/W Input- synchronous Synchronous read/write input. When LD is LOW, this input designates the access type (read when R/W is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times around the edge of K. C Input clock Positive input clock for output data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 10 for further details. C Input clock Negative input clock for output data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 10 for further details. K Input clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. K Input clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. [+] Feedback |
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