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CY7C1415KV18 Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY7C1415KV18
Description  36-Mbit QDR짰 II SRAM 4-Word Burst Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1415KV18 Datasheet(HTML) 8 Page - Cypress Semiconductor

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CY7C1411KV18, CY7C1426KV18
CY7C1413KV18, CY7C1415KV18
Document Number: 001-57826 Rev. *B
Page 8 of 33
CQ
Echo clock
CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks are shown in the Switching Characteristics on page 26.
CQ
Echo clock
CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks are shown in the Switching Characteristics on page 26.
ZQ
Input
Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
DOFF
Input
PLL turn off
 active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
is connected to a pull up through a 10 K
 or less pull-up resistor. The device behaves in QDR I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with QDR I timing.
TDO
Output
TDO for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/72M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/144M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/288M
N/A
Not connected to the die. Can be tied to any voltage level.
VREF
Input-
reference
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
VDD
Power supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the device.
VDDQ
Power supply Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Pin Name
I/O
Pin Description
[+] Feedback


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