CY7C1316KV18, CY7C1916KV18

CY7C1318KV18, CY7C1320KV18

Document Number: 001-58905 Rev. *C

Page 7 of 32

Pin Definitions

Pin Name

I/O

Pin Description

Input output-

synchronous

Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write

operations. These pins drive out the requested data when the read operation is active. Valid data is driven

out on the rising edge of both the C and C clocks during read operations or K and K when in single clock

CY7C1316KV18

 DQ

[7:0]

CY7C1916KV18

 DQ

[8:0]

CY7C1318KV18

 DQ

[17:0]

CY7C1320KV18

 DQ

[35:0]

LD

Input-

synchronous

Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition

includes address and read/write direction. All transactions operate on a burst of 2 data.

Input-

synchronous

Nibble Write Select 0, 1

 Active LOW (CY7C1316KV18 Only). Sampled on the rising edge of the K and

K clocks during write operations. Used to select which nibble is written into the device during the current

portion of the write operations. Nibbles not written remain unaltered.

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

ignores the corresponding nibble of data and it is not written into the device.

Input-

synchronous

Byte Write Select 0, 1, 2, and 3

 Active LOW. Sampled on the rising edge of the K and K clocks during

write operations. Used to select which byte is written into the device during the current portion of the write

operations. Bytes not written remain unaltered.

CY7C1916KV18

 BWS

CY7C1318KV18

 BWS

CY7C1320KV18

 BWS

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

ignores the corresponding byte of data and it is not written into the device.

A, A0

Input-

synchronous

Address Inputs. These address inputs are multiplexed for both read and write operations. Internally, the

device is organized as 2 M × 8 (2 arrays each of 1 M × 8) for CY7C1316KV18 and 2 M × 9 (2 arrays each

of 1 M × 9) for CY7C1916KV18, 1 M × 18 (2 arrays each of 512 K × 18) for CY7C1318KV18, and

512 K × 36 (2 arrays each of 256 K × 36) for CY7C1320KV18.

CY7C1316KV18 – Since the least significant bit of the address internally is a “0,” only 20 external address

inputs are needed to access the entire memory array.

CY7C1916KV18 – Since the least significant bit of the address internally is a “0,” only 20 external address

inputs are needed to access the entire memory array.

CY7C1318KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.

20 address inputs are needed to access the entire memory array.

CY7C1320KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.

19 address inputs are needed to access the entire memory array. All the address inputs are ignored when

the appropriate port is deselected.

R/W

Input-

synchronous

Synchronous Read or Write Input. When LD is LOW, this input designates the access type (read when

R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times

around edge of K.

C

Input clock

Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the

device. C and C can be used together to deskew the flight times of various devices on the board back to

the controller. See application example for further details.

C

Input clock

Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the

device. C and C can be used together to deskew the flight times of various devices on the board back to

the controller. See application example for further details.

K

Input clock

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and

K

Input clock

Negative Input Clock Input. K is used to capture synchronous data being presented to the device and to

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