CY7C1356C datasheet(9/32 Pages) CYPRESS

Part #	CY7C1356C

Description	9-Mbit (256 K 횞 36/512 K 횞 18) Pipelined SRAM with NoBL??Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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9 / 32 page

CY7C1354C, CY7C1356C

Document Number: 38-05538 Rev. *K

Page 9 of 32

The data written during the write operation is controlled by BW

(BWa,b,c,d for CY7C1354C and BWa,b for CY7C1356C) signals.

The CY7C1354C/CY7C1356C provides byte write capability that

is described in the Write Cycle Description table. Asserting the

write enable input (WE) with the selected byte write select (BW)

input will selectively write to only the desired bytes. Bytes not

selected during a byte write operation remain unaltered. A

synchronous self-timed write mechanism is provided to simplify

the write operations. Byte write capability is included to greatly

simplify read/modify/write sequences, which can be reduced to

simple byte write operations.

Because the CY7C1354C and CY7C1356C are common I/O

devices, data should not be driven into the device while the

outputs are active. The output enable (OE) can be deasserted

HIGH

before

presenting

data

to

the

DQ and DQP

(DQa,b,c,d/DQPa,b,c,d for CY7C1354C and DQa,b/DQPa,b for

CY7C1356C) inputs. Doing so will tristate the output drivers. As

a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for

CY7C1354C

and

DQa,b/DQPa,b for CY7C1356C) are

automatically tristated during the data portion of a write cycle,

regardless of the state of OE.

Burst Write Accesses

The CY7C1354C/CY7C1356C has an on-chip burst counter that

enables the user the ability to supply a single address and

conduct up to four write operations without reasserting the

address inputs. ADV/LD must be driven LOW to load the initial

address, as described in Single Write Accesses on page 8.

When ADV/LD is driven HIGH on the subsequent clock rise, the

chip enables (CE1, CE2, and CE3) and WE inputs are ignored

and the burst counter is incremented. The correct BW (BWa,b,c,d

for CY7C1354C and BWa,b for CY7C1356C) inputs must be

driven in each cycle of the burst write to write the correct bytes

of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation ‘sleep’ mode. Two clock

cycles are required to enter into or exit from this ‘sleep’ mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered valid

nor is the completion of the operation guaranteed. The device

must be deselected prior to entering the “sleep” mode. CE1, CE2,

and CE3, must remain inactive for the duration of tZZREC after the

ZZ input returns LOW.

Table 1. Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

Second

Address

Third

Address

Fourth

Address

A1, A0

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Table 2. Linear Burst Address Table (MODE = GND)

First

Address

Second

Address

Third

Address

Fourth

Address

A1, A0

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

Table 3. ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min

Max

Unit

IDDZZ

Sleep mode standby current

ZZ

 VDD 0.2 V

–

50

mA

tZZS

Device operation to ZZ

ZZ

VDD  0.2 V

–

2tCYC

ns

tZZREC

ZZ recovery time

ZZ

0.2 V

2tCYC

–ns

tZZI

ZZ active to sleep current

This parameter is sampled

–

2tCYC

ns

tRZZI

ZZ Inactive to exit sleep current

This parameter is sampled

0

–

ns

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