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CY7C1312KV18 Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY7C1312KV18 Datasheet(HTML) 10 Page - Cypress Semiconductor |
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10 / 32 page  CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 Document Number: 001-58903 Rev. *C Page 10 of 32 Echo Clocks Echo clocks are provided on the QDR II to simplify data capture on high speed systems. Two echo clocks are generated by the QDR II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free running clocks and are synchronized to the output clock of the QDR II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 25. PLL These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the PLL is locked after 20 s of stable clock. The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 s after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in QDR I mode (with one cycle latency and a longer access time). Application Example Figure 1 shows two QDR II used in an application. Figure 1. Application Example R = 250 ohms Vt R R = 250 ohms Vt Vt R Vt = Vddq/2 R = 50 ohms R CC# D A SRAM #2 R P S # W P S # B W S # ZQ CQ/CQ# Q K# CC# D A K SRAM #1 R P S # W P S # B W S # ZQ CQ/CQ# Q K# BUS MASTER (CPU or ASIC) DATA IN DATA OUT Address RPS# WPS# BWS# Source K Source K# Delayed K Delayed K# CLKIN/CLKIN# K [+] Feedback |
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