CY7C1148KV18-450BZXC datasheet(2/29 Pages) CYPRESS

Part #	CY7C1148KV18-450BZXC

Description	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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2 / 29 page

CY7C1146KV18, CY7C1157KV18

CY7C1148KV18, CY7C1150KV18

Document Number: 001-58912 Rev. *C

Page 2 of 29

Logic Block Diagram (CY7C1146KV18)

Logic Block Diagram (CY7C1157KV18)

Write

Reg

Write

Reg

CLK

A(19:0)

Gen.

K

Control

Logic

Address

Register

Read Data Reg.

R/W

Output

Logic

Reg.

8

16

8

NWS[1:0]

VREF

8

20

8

LD

Control

R/W

DOFF

8

DQ[7:0]

8

CQ

QVLD

Write

Reg

Write

Reg

CLK

A(19:0)

Gen.

K

Control

Logic

Address

Register

Read Data Reg.

R/W

Output

Logic

Reg.

9

18

9

BWS[0]

VREF

9

20

9

LD

Control

R/W

DOFF

9

DQ[8:0]

9

CQ

QVLD

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CY7C1148KV18-450BZXC Datasheet(PDF) 2 Page - Cypress Semiconductor

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