CY7C1146KV18 datasheet(17/29 Pages) CYPRESS

Part #	CY7C1146KV18

Description	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

Download	29 Pages

Scroll/Zoom	100%

Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

Logo

17 / 29 page

CY7C1146KV18, CY7C1157KV18

CY7C1148KV18, CY7C1150KV18

Document Number: 001-58912 Rev. *C

Page 17 of 29

TAP AC Switching Characteristics

Over the Operating Range [14, 15]

Parameter

Description

Min

Max

Unit

tTCYC

TCK Clock Cycle Time

50

–

ns

tTF

TCK Clock Frequency

–

20

MHz

tTH

TCK Clock HIGH

20

–

ns

tTL

TCK Clock LOW

20

–

ns

Setup Times

tTMSS

TMS Setup to TCK Clock Rise

5

–

ns

tTDIS

TDI Setup to TCK Clock Rise

5

–

ns

tCS

Capture Setup to TCK Rise

5

–

ns

Hold Times

tTMSH

TMS Hold after TCK Clock Rise

5

–

ns

tTDIH

TDI Hold after Clock Rise

5

–

ns

tCH

Capture Hold after Clock Rise

5

–

ns

Output Times

tTDOV

TCK Clock LOW to TDO Valid

–

10

ns

tTDOX

TCK Clock LOW to TDO Invalid

0

–

ns

TAP Timing and Test Conditions

Figure 2 shows the TAP timing and test conditions. [15]

Figure 2. TAP Timing and Test Conditions

tTL

tTH

(a)

TDO

CL = 20 pF

Z0 = 50 

GND

0.9 V

50



1.8 V

0 V

All Input Pulses

0.9 V

Test Clock

Test Mode Select

TCK

TMS

Test Data In

TDI

Test Data Out

tTCYC

tTMSH

tTMSS

tTDIS

tTDIH

tTDOV

tTDOX

TDO

Notes

14. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

15. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

[+] Feedback

Similar Part No. - CY7C1146KV18

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C11461KV18	854Kb / 29P	18-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C1146V18	1Mb / 27P	18-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C1146V18-333BZC	1Mb / 27P	18-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C1146V18-333BZI	1Mb / 27P	18-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C1146V18-333BZXC	1Mb / 27P	18-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

More results

Similar Description - CY7C1146KV18

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C1166KV18	874Kb / 29P	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C11661KV18	754Kb / 26P	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1668KV18	771Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1268KV18	871Kb / 28P	36-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1166V18	1Mb / 27P	18-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C2168KV18	879Kb / 29P	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
	CY7C1268XV18	900Kb / 28P	36-Mbit DDR II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1648KV18	857Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C1548KV18	844Kb / 29P	72-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C1566KV18	921Kb / 31P	72-Mbit DDR II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

More results

CY7C1146KV18 Datasheet(PDF) 17 Page - Cypress Semiconductor

CY7C1146KV18 Datasheet(HTML) 17 Page - Cypress Semiconductor

Similar Part No. - CY7C1146KV18

Similar Description - CY7C1146KV18

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL