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CY7C1146KV18 Datasheet(PDF) 17 Page - Cypress Semiconductor |
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CY7C1146KV18 Datasheet(HTML) 17 Page - Cypress Semiconductor |
17 / 29 page CY7C1146KV18, CY7C1157KV18 CY7C1148KV18, CY7C1150KV18 Document Number: 001-58912 Rev. *C Page 17 of 29 TAP AC Switching Characteristics Over the Operating Range [14, 15] Parameter Description Min Max Unit tTCYC TCK Clock Cycle Time 50 – ns tTF TCK Clock Frequency – 20 MHz tTH TCK Clock HIGH 20 – ns tTL TCK Clock LOW 20 – ns Setup Times tTMSS TMS Setup to TCK Clock Rise 5 – ns tTDIS TDI Setup to TCK Clock Rise 5 – ns tCS Capture Setup to TCK Rise 5 – ns Hold Times tTMSH TMS Hold after TCK Clock Rise 5 – ns tTDIH TDI Hold after Clock Rise 5 – ns tCH Capture Hold after Clock Rise 5 – ns Output Times tTDOV TCK Clock LOW to TDO Valid – 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 – ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions. [15] Figure 2. TAP Timing and Test Conditions tTL tTH (a) TDO CL = 20 pF Z0 = 50 GND 0.9 V 50 1.8 V 0 V All Input Pulses 0.9 V Test Clock Test Mode Select TCK TMS Test Data In TDI Test Data Out tTCYC tTMSH tTMSS tTDIS tTDIH tTDOV tTDOX TDO Notes 14. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 15. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. [+] Feedback |
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