CY2XL11

100 MHz LVDS Clock Generator

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document Number: 001-42886 Rev. *F

Revised March 18, 2011

Features

(637 kHz to 10 MHz): 0.53 ps (typical)

Functional Description

The CY2XL11 is a PLL based high performance clock generator

with a crystal oscillator interface and one LVDS output pair. It is

optimized to generate PCI Express, FC, and other high-

performance clock frequencies. It also produces an output

frequency that is four times the crystal frequency. It uses

Cypress’s low-noise VCO technology to achieve less than 1 ps

typical RMS phase jitter, that meets high-performance systems’

jitter requirements.

Output

Divider

OE

Crystal

Oscillator

CLK#

Low-Noise PLL

CLK

XOUT

XIN

External

Crystal

Logic Block Diagram

Pinouts

Figure 1. Pin Diagram - 8-Pin TSSOP

1

2

36

7

8

XOUT

XIN

OE

VSS

VDD

CLK#

45

VDD

CLK

Table 1. Pin Definition – 8-Pin TSSOP

Pin Number

Pin Name

I/O Type

Description

1, 8

VDD

Power

3.3 V or 2.5 V power supply. All supply current flows through pin 1

2

VSS

Power

Ground

3, 4

XOUT, XIN

XTAL output and input

Parallel resonant crystal interface

5

OE

CMOS input

Output enable. When HIGH, the output is enabled. When LOW, the

output is high-impedance

6,7

CLK#, CLK

LVDS output

Differential clock output

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