CY2XP41

Document #: 001-48923 Rev. *C

Page 6 of 10

Measurement Definitions

Figure 2. Output Load AC Test Circuit

Figure 3. RMS Phase Jitter

Figure 4. Output Duty Cycle

Figure 5. Output Rise and Fall Time and Peak-Peak Voltage Swing

Measurement

Point

CLK

CLK#

3.3 V

Z=50

Ω

Z=50

Ω

3.3 V

110

Ω

110

Ω

62

Ω

62

Ω

2pF

2pF

Noise Power

Offset Frequency

1.5 MHz

10 MHz

Phase Noise

Phase Noise Mask

40 dB/Decade

20 dB/Decade

RMS Jitter =

CLK

T

PW

T

PERIOD

T

T

PW

T

PERIOD

CLK#

80%

20%

CLK

CLK#

VSS

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