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CY2XP41 Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY2XP41
Description  Crystal to LVPECL Clock Generator
Download  10 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2XP41 Datasheet(HTML) 4 Page - Cypress Semiconductor

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CY2XP41
Document #: 001-48923 Rev. *C
Page 4 of 10
Frequency Table
Input
Output Frequency (MHz)
Input Xtal Frequency (MHz)
FS
25
0
62.5
25
1
75.0
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply Voltage
–0.5
4.4
V
VIN
[1.]
Input Voltage, DC
Relative to VSS
–0.5
VDD + 0.5
V
TS
Temperature, Storage
Non Functional
–65
150
°C
TJ
Temperature, Junction
135
°C
ESDHBM
ESD Protection (Human Body Model) JEDEC STD 22-A114-B
2000
V
UL–94
Flammability Rating
At 1/8 in.
V–0
Θ
JA
[2]
Thermal Resistance, Junction to
Ambient
0 m/s airflow
100
°C/W
1 m/s airflow
91
2.5 m/s airflow
87
Operating Conditions
Parameter
Description
Min
Max
Unit
VDD
3.3 V Supply Voltage
3.135
3.465
V
TA
Ambient Temperature, Commercial
0
70
°C
TPU
Power up time for all VDD to reach minimum specified voltage (ensure power
ramps are monotonic)
0.05
500
ms
Electrical Characteristics for Input
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VIL
Input Low Voltage , FS
0.3*VDD
V
VIH
Input High Voltage, FS
0.7*VDD
––
V
IIL
Input Low Current , FS
FS = VSS
–50
µA
IIH
Input High Current, FS
FS = VDD
––
115
µA
CIN
[3]
Input Capacitance, FS
15
pF
CINX
[3]
Input Capacitance, XIN & XOUT
4.5
pF
DC Electrical Characteristics for Power Supplies
Parameter
Description
Min
Typ
Max
Unit
IDD
Power Supply Current with output unterminated
125
mA
IDDT
Power Supply Current with output terminated
180
mA
Note
1. The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metallization. No vias are included in the model.
3. Not 100% tested, guaranteed by design and characterization.
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