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CY8C22345 Datasheet(PDF) 18 Page - Cypress Semiconductor

Part # CY8C22345
Description  PSoC Programmable System-on-Chip
Download  35 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C22345 Datasheet(HTML) 18 Page - Cypress Semiconductor

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CY8C21345
CY8C22345, CY8C22545
Document Number: 001-43084 Rev. *L
Page 18 of 35
SAR10 ADC DC Specifications
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T
A ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V or 3.3V at 25°C and are for design
guidance only.
DC Analog Mux Bus Specifications
Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T
A ≤ 85°C or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V or 3.3V at 25°C and are for design
guidance only.
DC POR and LVD Specifications
Table 16 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T
A ≤ 85°C or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V or 3.3V at 25°C and are for design
guidance only.
Table 14. SAR10 ADC DC Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vadcvref
Reference voltage at pin P2[5] when configured
as ADC reference voltage
3.0
5.25
V
When VREF is buffered inside
ADC, the voltage level at P2[5]
(when configured as ADC
reference voltage) must be
always maintained to be at least
300 mV less than the chip supply
voltage level on Vdd pin.
(Vadcvref < Vdd)
Iadcvref
Current when P2[5] is configured as ADC VREF
-
0.5
mA
Disables the internal voltage
reference buffer
INL at 10 bits
Integral Nonlinearity
-2.5
–2.5
LSB
For VDD ≥ 3.0V and Vref ≥ 3.0V
-5.0
–5.0
LSB
For VDD < 3.0V or Vref < 3.0V
DNL at 10 bits
Differential Nonlinearity
-1.5
–1.5
LSB
For VDD≥ 3.0V and Vref ≥ 3.0V
-4.0
–4.0
LSB
For VDD < 3.0V or Vref < 3.0V
SPS
Sample per second
150
ksps
Resolution 10 bits
Table 15. DC Analog Mux Bus Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
RSW
Switch Resistance to Common Analog Bus
400
Ω
Vdd
≥ 3.00
Rgnd
Resistance of Initialization Switch to gnd
800
Ω
Table 16. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VPPOR1
VPPOR2
Vdd Value for PPOR Trip
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–2.82
4.55
2.95
4.70
V
V
Vdd must be greater than or
equal to 3.0V during startup,
reset from the XRES pin, or
reset from Watchdog.
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.95
3.06
4.37
4.50
4.62
4.71
3.02
3.13
4.48
4.64
4.73
4.81
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
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