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LC89515K Datasheet(PDF) 4 Page - Sanyo Semicon Device

Part No. LC89515K
Description  CD-ROM/CD-I Error Correction/ Host Interface LSI
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Maker  SANYO [Sanyo Semicon Device]
Homepage  https://www.sanyo-av.com/us/
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LC89515K Datasheet(HTML) 4 Page - Sanyo Semicon Device

   
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Furthermore, the LC89515K SELDRQ pin can be used to perform DRQ (data request) transfers. This is a technique
in which transfers are performed by the host outputting HRD pulses according to a data request signal output from
the LC89515K and is similar to DMA controller operation.
When the last byte of the count specified by the control microprocessor is read, EOP goes active while the read pulse
is output. Also DTEN is set inactive after this time. Next, a transfer complete interrupt is issued to inform the control
microprocessor that the transfer to the host has completed.
The LC89515K control microprocessor can pass the decoding result for the data requested by the host and the CD-
ROM drive status information to the host by writing to the LC89515K internal status registers. The status registers
are a 12-byte FIFO, and the host reads out data while the STEN signal is low. The STEN signal goes high when the
last byte is read. The LC89515K has nothing to do with the content of the status registers.
Since the command and status registers are neither interpreted nor executed by the LC89515K, the LC89515K user
can define the command and status data as unrestricted protocols between the host and the microprocessor. This
allows CD-ROM application systems to be designed without restriction, and also allows an existing system to be
replaced by a system using the LC89515K.
4. Points Common to All Blocks
The LC89515K performs data input and decoding at the same time in a pipelined manner. Also, writes of input data
to the buffer RAM, writes of data to be decoded, and reads to the buffer RAM for transfers to the host all proceed at
the same time with synchronization always being maintained by the LC89515K. Therefore there is no need for the
control microprocessor to be concerned with which master (system block) is accessing the buffer RAM.
5. Register Table
Read
Note: The values of the shaded bits are ignored.
No. 4272-4/6
LC89515K
RS
AR
No.
Symbol
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
0
AR
0
0
0
0
A3
A2
A1
A0
0000
R0
COMIN
msb
lsb
0001
R1
IFSTAT
CMDI
DTEI
DECI
1
DTBSY
STBSY
DTEN
STEN
0010
R2
DBCL
B7
B6
B5
B4
B3
B2
B1
B0
0011
R3
DBCH
DTEI
DTEI
DTEI
DTEI
B11
B10
B9
B8
0100
R4
HEAD0
msb
lsb
0101
R5
HEAD1
msb
lsb
0110
R6
HEAD2
msb
lsb
1
0111
R7
HEAD3
msb
lsb
1000
R8
PTL
A7
A6
A5
A4
A3
A2
A1
A0
1001
R9
PTH
A15
A14
A13
A12
A11
A10
A9
A8
1010
R10
WAL
A7
A6
A5
A4
A3
A2
A1
A0
1011
R11
WAH
A15
A14
A13
A12
A11
A10
A9
A8
1100
R12
STAT0
CRCOK
ILSYNC
NOSYNC
LBLK
WSHORT
SBLK
ERABLK
UCEBLK
1101
R13
STAT1
MINERA
SECERA
BLKERA
MODERA
SH0ERA
SH1ERA
SH2ERA
SH3ERA
1110
R14
STAT2
RMOD3
RMOD2
RMOD1
RMOD0
MODE
NOCOR
RFORM1
RFORM0
1111
R15
STAT3
VALST
WLONG
CBLK


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