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LC89515K Datasheet(PDF) 3 Page - Sanyo Semicon Device

Part No. LC89515K
Description  CD-ROM/CD-I Error Correction/ Host Interface LSI
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Maker  SANYO [Sanyo Semicon Device]
Homepage  https://www.sanyo-av.com/us/
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LC89515K Datasheet(HTML) 3 Page - Sanyo Semicon Device

   
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Block Functions
The LC89515K consist of three major blocks. This section describes those blocks.
1. CD Player Interface and Data Input Block
This LSI can handle three serial input formats selectable by setting external pin voltages. That is, differences in CD
player serial data formats can be compensated for by setting the CSEL and LMSEL inputs.
Internal operations are synchronized with the input data in block (sector) units using a synchronization detector
circuit. The synchronization circuit not only uses pattern detection on the externally input data, but also performs
synchronization protection with a synchronization signal interpolation circuit. These two synchronization systems
can be turned on or off under program control.
The input data is written to a buffer RAM in 8-bit units after passing through a descrambling circuit. The C2 pointer
(error flag) from the CD player is also written to RAM at this time. Although applications that use the C2 pointer
must provide a 9-bit RAM, the C2 pointer may be omitted and such applications need only provide an 8-bit RAM.
However, note that erasure correction cannot be performed if the C2 pointer is not used.
All input data, including sync, header, subheader and parity (2352 bytes) is stored in RAM in the order received from
the CD player in its entirety.
Furthermore, the LC89515K provides an output pin (MCK) for use with the CD LSI’s oscillator input pin. Therefore,
the number of oscillator elements in the end product can be reduced by selecting the LC89515K master clock
frequency to be twice the CD LSI clock frequency.
2. Error Detection and Correction Block
Error correction code decoding is performed after a full block (sector: 2352 bytes) of data has been stored in RAM.
The LC89515K error correction function operates in real time completely internally. The system software merely
waits for that processing to complete. Furthermore, buffering of data from the CD and transfer to the host computer
are performed simultaneously. That is, the LC89515K can transfer to the host computer data that has been error
corrected without any reduction in the data transfer rate from the CD.
The error correction technique not only consists of error detection and correction, but also supports combination with
erasure correction referencing the C2 pointer. This means that data with high reliability is acquired. The error
detection and correction process can correct single symbol errors, and can correct two symbol errors when combined
with erasure correction.
Furthermore, the error correction algorithm is programmable, and the LC89515K can be instructed to perform a wide
variety of procedures, such as iterative correction or QP/PQ correction, to improve data reliability.
After decoding the error correction codes (ECC), a 32-bit CRC error check is performed using the error detection
codes (EDC). During the CRC check the header and subheader are loaded into LC89515K internal registers.
After completing the CRC check the LC89515K issues a decoding complete interrupt to the control microprocessor.
The microprocessor then reads the header and subheader of the decoded block, the start address of the block in buffer
RAM, and a decoding result status indicator from the LC89515K.
3. Host Interface Block
The data transfer rate to the host computer has been improved significantly, to 2.3 MB/s, and since the amount of
buffering RAM has been increased to 64 kB, up to 27 sectors (blocks) of the CD ROM drive can be stored. This
memory can also be used as a disk cache memory.
The host interface provides an 8-byte FIFO for receiving commands from the host. The host can write up to 8 bytes
of commands at one time by asserting the HWR signal. When the host writes to the FIFO, the LC89515K issues a
command interrupt to the control microprocessor. Here, the commands written to the 8-byte FIFO are never
interpreted by the LC89515K.
When transferring data to the host, the control microprocessor writes the number of bytes to transfer and the start
address in buffer RAM of the block to be transferred. Then, it performs a write operation to the transfer start trigger
register. This causes the DTEN pin to go low and informs the host of the data transfer start. While the DTEN pin is
low the host reads data items one after another by generating HRD read pulses. If the host reads extremely rapidly,
i.e., over about 2.3 MB/s, then the LC89515K will output a WAIT signal. The host must not set HRD high while
WAIT is low. During this single block transfer operation, the microprocessor does nothing other than waiting for the
transfer complete interrupt that occurs when the transfer is done.
No. 4272-3/6
LC89515K


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