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LC895125W Datasheet(PDF) 9 Page - Sanyo Semicon Device |
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LC895125W Datasheet(HTML) 9 Page - Sanyo Semicon Device |
9 / 11 page Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Note: 1. NC pins must be left open. Do not connect any signal to these pins. 2. Pin names that start with Z are negative-logic signals. 3. VSS0 is the logic system ground and VSS1 is the SCSI interface ground. 4. Applications that use DRAM must insert resistors in the CAS and RAS lines, connect capacitors between these lines and ground, and take any other measures necessary to prevent undershoot in the DRAM related circuits. 5. Since these circuits include buffers that sink 48 mA, adequate noise prevention measures must be applied. No. 5241-9/11 LC895125Q, 895125W Pin No. Symbol Type Function 101 SEL B SCSI connection 102 C/D B 103 VSS1 P 104 REQ B SCSI connection 105 I/O B 106 VSS1 P 107 VDD P 108 VSS0 P 109 VDD P 110 VSS0 P 111 NC 112 VSS0 P 113 VSS0 P 114 VSS0 P 115 NC 116 NC 117 C2PO I 118 SDATA I CD DSP interface 119 BCK I 120 LRCK I 121 MCK O Outputs the XTALCK0 frequency, or that frequency divided by 2. 122 VSS0 P 123 EXCK O 124 WFCK I Subcode I/O 125 SBSO I 126 VDD P 127 VSS0 P 128 SCOR I Subcode I/O 129 VSS0 P 130 NC 131 ZRAS0 O Buffer RAM RAS signal output pin 0 (Normally, pin 0 is used) 132 ZRAS1 O Buffer RAM RAS signal output pin 1 133 ZCAS0 O Buffer RAM CAS signal output pin 0 (Normally, pin 0 is used) 134 ZCAS1 O Buffer RAM CAS signal output pin 1 135 ZOE O Buffer RAM output enable 136 ZUWE O Buffer RAM upper write enable 137 ZLWE O Buffer RAM lower write enable 138 VSS0 P 139 RA0 O 140 RA1 O 141 RA2 O Buffer RAM address signal outputs 142 RA3 O 143 RA4 O 144 VDD P |
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