Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

ZL9101M Datasheet(PDF) 12 Page - Intersil Corporation

Part No. ZL9101M
Description  Digital DC/DC PMBus 12A Module
Download  17 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo 

ZL9101M Datasheet(HTML) 12 Page - Intersil Corporation

Zoom Inzoom in Zoom Outzoom out
 12 / 17 page
background image
ZL9101M
12
FN7669.1
January 26, 2011
Digital-DC Bus
The Digital-DC Communications (DDC) bus is used to
communicate between Zilker Labs Digital-DC modules and
devices. This dedicated bus provides the communication channel
between devices for features such as sequencing, fault
spreading, and current sharing. The DDC pin on all Digital-DC
devices in an application should be connected together. A pull-up
resistor is required on the DDC bus in order to guarantee the rise
time as follows:
where RPU is the DDC bus pull-up resistance and CLOAD is the
bus loading. The pull-up resistor may be tied to an external 3.3V
or 5V supply as long as this voltage is present prior to or during
device power-up. As rules of thumb, each device connected to the
DDC bus presents approximately 10pF of capacitive loading, and
each inch of FR4 PCB trace introduces approximately 2pF. The
ideal design will use a central pull-up resistor that is well-
matched to the total load capacitance. The minimum pull-up
resistance should be limited to a value that enables any device to
assert the bus to a voltage that will ensure a logic 0 (typically
0.8V at the device monitoring point) given the pull-up voltage and
the pull-down current capability of the ZL9101M (nominally
4mA).
Phase Spreading
When multiple point of load converters share a common DC
input supply, it is desirable to adjust the clock phase offset of
each device such that not all devices start to switch
simultaneously. Setting each converter to start its switching cycle
at a different point in time can dramatically reduce input
capacitance requirements and efficiency losses. Since the peak
current drawn from the input supply is effectively spread out over
a period of time, the peak current drawn at any given moment is
reduced and the power losses proportional to the IRMS2 are
reduced dramatically.
In order to enable phase spreading, all converters must be
synchronized to the same switching clock.
The phase offset of each device may also be set to any value
between 0° and 360° in 22.5° increments via the I2C/SMBus
interface. Refer to Application Note AN2033 for further details.
Output Sequencing
A group of Digital-DC modules or devices may be configured to power
up in a predetermined sequence. This feature is especially useful when
powering advanced processors, FPGAs, and ASICs that require one
supply to reach its operating voltage prior to another supply reaching its
operating voltage in order to avoid latch-up from occurring. Multi-device
sequencing can be achieved by configuring each device through the
I2C/SMBus interface.
Multiple device sequencing is configured by issuing PMBus
commands to assign the preceding device in the sequencing
chain as well as the device that will follow in the sequencing
chain.
The Enable pins of all devices in a sequencing group must be tied
together and driven high to initiate a sequenced turn-on of the
group. Enable must be driven low to initiate a sequenced turnoff
of the group.
Refer to Application Note AN2033 for details on sequencing via
the I2C/SMBus interface.
Fault Spreading
Digital DC modules and devices can be configured to broadcast a fault
event over the DDC bus to the other devices in the group. When a non-
destructive fault occurs and the device is configured to shut down on a
fault, the device will shut down and broadcast the fault event over the
DDC bus. The other devices on the DDC bus will shut down together if
configured to do so, and will attempt to re-start in their prescribed order
if configured to do so.
Active Current Sharing
Paralleling multiple ZL9101M modules can be used to increase
the output current capability of a single power rail. By connecting
the DDC pins of each module together and configuring the
modules as a current sharing rail, the units will share the current
equally within a few percent.
Figure 11 illustrates a typical connection for two modules.
The ZL9101M uses a low-bandwidth, first-order digital current
sharing technique to balance the unequal module output loading
by aligning the load lines of member modules to a reference
module.
Droop resistance is used to add artificial resistance in the output
voltage path to control the slope of the load line curve,
61.9
0x2C
68.1
0x2D
75
0x2E
82.5
0x2F
90.9
0x30
100
0x31
TABLE 2. SMBus ADDRESS RESISTOR SELECTION
(Continued)
RSA0
SMBus Address
Rise Time
R
PU
∗C
LOAD
1
μs
=
(EQ. 1)
FIGURE 11. CURRENT SHARING GROUP
ZL
VOUT
ZL
VIN
COUT
CIN
COUT
CIN
DDC
DDC
3.3V - 5V


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn