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ZL9101M Datasheet(PDF) 10 Page - Intersil Corporation

Part No. ZL9101M
Description  Digital DC/DC PMBus 12A Module
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ZL9101M Datasheet(HTML) 10 Page - Intersil Corporation

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ZL9101M
10
FN7669.1
January 26, 2011
Adaptive Diode Emulation
Adaptive diode emulation mode turns off the low-side FET gate
drive at low load currents to prevent the inductor current from
going negative, reducing the energy losses and increasing overall
efficiency. Diode emulation is available to single-phase devices
only.
Note: the overall bandwidth of the device may be reduced when
in diode emulation mode. It is recommended that diode
emulation is disabled prior to applying significant load steps.
Input Undervoltage Lockout
The input undervoltage lockout (UVLO) prevents the ZL9101M
from operating when the input falls below a preset threshold,
indicating the input supply is out of its specified range. The UVLO
threshold (VUVLO) can be set between 2.85V and 16V using the
I2C/SMBus interface.
Once an input undervoltage fault condition occurs, the device
can respond in a number of ways as follows:
1. Continue operating without interruption.
2. Continue operating for a given delay period, followed by
shutdown if the fault still exists. The device will remain in
shutdown until instructed to restart.
3. Initiate an immediate shutdown until the fault has been
cleared. The user can select a specific number of retry
attempts.
The default response from a UVLO fault is an immediate
shutdown of the module. The controller will continuously check
for the presence of the fault condition. If the fault condition is no
longer present, the ZL9101M will be re-enabled.
Please refer to Application Note AN2033 for details on how to
configure the UVLO threshold or to select specific UVLO fault
response options via the I2C/SMBus interface.
Output Overvoltage Protection
The ZL9101M offers an internal output overvoltage protection circuit
that can be used to protect sensitive load circuitry from being subjected
to a voltage higher than its prescribed limits. A hardware comparator is
used to compare the actual output voltage (seen at the FB+ pin) to a
threshold set to 15% higher than the target output voltage (the default
setting). If the FB+ voltage exceeds this threshold, the PG pin will
de-assert and the controller can then respond in a number of ways as
follows:
1. Initiate an immediate shutdown until the fault has been
cleared. The user can select a specific number of retry
attempts.
2. Turn off the high-side MOSFET and turn on the low-side
MOSFET. The low-side MOSFET remains ON until the device
attempts a restart.
The default response from an overvoltage fault is to immediately
shut down. The controller will continuously check for the
presence of the fault condition, and when the fault condition no
longer exists the device will be re-enabled.
For continuous overvoltage protection when operating from an
external clock, the only allowed response is an immediate
shutdown.
Please refer to Application Note AN2033 for details on how to
select specific overvoltage fault response options via I2C/SMBus.
Output Pre-Bias Protection
An output pre-bias condition exists when an externally applied
voltage is present on a power supply’s output before the power
supply’s control IC is enabled. Certain applications require that
the converter not be allowed to sink current during start up if a
pre-bias condition exists at the output. The ZL9101M provides
pre-bias protection by sampling the output voltage prior to
initiating an output ramp.
If a pre-bias voltage lower than the target voltage exists after the
pre-configured delay period has expired, the target voltage is set
to match the existing pre-bias voltage and both drivers are
enabled. The output voltage is then ramped to the final
regulation value at the preconfigured ramp rate.
The actual time the output will take to ramp from the pre-bias
voltage to the target voltage will vary depending on the pre-bias
voltage but the total time elapsed from when the delay period
expires and when the output reaches its target value will match
the pre-configured ramp time. See Figure 10.
If a pre-bias voltage higher than the target voltage exists after the
pre-configured delay period has expired, the target voltage is set
to match the existing pre-bias voltage and both drivers are
enabled with a PWM duty cycle that would ideally create the
pre-bias voltage.
Once the pre-configured soft-start ramp period has expired, the
PG pin will be asserted (assuming the pre-bias voltage is not
higher than the overvoltage limit). The PWM will then adjust its
FIGURE 10. OUTPUT RESPONSES TO PRE-BIAS VOLTAGES


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