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HT1621 Datasheet(PDF) 8 Page - Holtek Semiconductor Inc

Part No. HT1621
Description  RAM Mapping 324 LCD Controller for I/O MCU
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Maker  HOLTEK [Holtek Semiconductor Inc]
Homepage  http://www.holtek.com
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HT1621 Datasheet(HTML) 8 Page - Holtek Semiconductor Inc

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HT1621/HT1621G
Rev. 2.90
8
November 9, 2010
PATENTED
Functional Description
Display Memory
- RAM
The static display memory (RAM) is organized into 32
´4
bits and stores the displayed data. The contents of the
RAM are directly mapped to the contents of the LCD
driver. Data in the RAM can be accessed by the READ,
WRITE, and READ-MODIFY-WRITE commands. The
following is a mapping from the RAM to the LCD pattern:
System Oscillator
The HT1621 system clock is used to generate the time
base/Watchdog Timer (WDT) clock frequency, LCD
driving clock, and tone frequency. The source of the
clock may be from an on-chip RC oscillator (256kHz), a
crystal oscillator (32.768kHz), or an external 256kHz
clock by the S/W setting. The configuration of the sys-
tem oscillator is as shown. After the SYS DIS command
is executed, the system clock will stop and the LCD bias
generator will turn off. That command is, however, avail-
able only for the on-chip RC oscillator or for the crystal
oscillator. Once the system clock stops, the LCD display
will become blank, and the time base/WDT lose its func-
tion as well.
The LCD OFF command is used to turn the LCD bias
generator off. After the LCD bias generator switches off
by issuing the LCD OFF command, using the SYS DIS
command reduces power consumption, serving as a
system power down command. But if the external clock
source is chosen as the system clock, using the SYS
DIS command can neither turn the oscillator off nor
carry out the power down mode. The crystal oscillator
option can be applied to connect an external frequency
source of 32kHz to the OSCI pin. In this case, the sys-
tem fails to enter the power down mode, similar to the
case in the external 256kHz clock source operation. At
the initial system power on, the HT1621 is at the SYS
DIS state.
Time Base and Watchdog Timer (WDT)
The time base generator is comprised by an 8-stage
count-up ripple counter and is designed to generate an
accurate time base. The watch dog timer (WDT), on the
other hand, is composed of an 8-stage time base gener-
ator along with a 2-stage count-up counter, and is de-
signed to break the host controller or other subsystems
from abnormal states such as unknown or unwanted
jump, execution errors, etc. The WDT time-out will result
in the setting of an internal WDT time-out flag. The out-
puts of the time base generator and of the WDT time-out
flag can be connected to the IRQ output by a command
option. There are totally eight frequency sources avail-
able for the time base generator and the WDT clock.
The frequency is calculated by the following equation.
fWDT =
32kHz
2
n
where the value of n ranges from 0 to 7 by command op-
tions. The 32kHz in the above equation indicates that
the source of the system frequency is derived from a
crystal oscillator of 32.768kHz, an on-chip oscillator
(256kHz), or an external frequency of 256kHz.
If an on-chip oscillator (256kHz) or an external 256kHz
frequency is chosen as the source of the system fre-
quency, the frequency source is by default prescaled to
32kHz by a 3-stage prescaler. Employing both the time
base generator and the WDT related commands, one
should be careful since the time base generator and
WDT share the same 8-stage counter. For example, in-
voking the WDT DIS command disables the time base
generator whereas executing the WDT EN command
not only enables the time base generator but activates
the WDT time-out flag output (connect the WDT
S E G 0
S E G 1
S E G 2
S E G 3
S E G 3 1
C O M 0
C O M 1
C O M 2
C O M 3
D 3
D 2
D 1
D 0
D a t a
A d d r
3 1
0
1
2
3
A d d r e s s 6 b i t s
( A 5 , A 4 , . . . , A 0 )
D a t a 4 b i t s
( D 3 , D 2 , D 1 , D 0 )
RAM Mapping
1 / 8
O S C I
O S C O
C r y s t a l O s c i l l a t o r
3 2 7 6 8 H z
E x t e r n a l C l o c k S o u r c e
2 5 6 k H z
O n - c h i p R C O s c i l l a t o r
2 5 6 k H z
S y s t e m
C l o c k
System Oscillator Configuration


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