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CYWUSB6953 Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CYWUSB6953 Datasheet(HTML) 8 Page - Cypress Semiconductor |
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8 / 68 page  CYRF69103 Document #: 001-07611 Rev *F Page 8 of 68 8.3.2 Link Layer Modes The CYRF69103 IC device supports the following data packet framing features: SOP – Packets begin with a 2-symbol Start of Packet (SOP) marker. This is required in GFSK and 8DR modes, but is optional in DDR mode and is not supported in SDR mode. If framing is disabled then an SOP event is inferred whenever two successive correlations are detected. The SOP_CODE_ADR code used for the SOP is different from that used for the “body” of the packet, and if desired may be a different length. SOP must be configured to be the same length on both sides of the link. EOP – There are two options for detecting the end of a packet. If SOP is enabled, then a packet length field may be enabled. GFSK and 8DR must enable the length field. This is the first 8 bits after the SOP symbol, and is transmitted at the payload data rate. If the length field is enabled, an End of Packet (EOP) condition is inferred after reception of the number of bytes defined in the length field, plus two bytes for the CRC16 (if enabled). The alternative to using the length field is to infer an EOP condition from a configurable number of successive non correlations; this option is not available in GFSK mode and is only recommended when using SDR mode. CRC16 – The device may be configured to append a 16-bit CRC16 to each packet. The CRC16 uses the USB CRC polynomial with the added programmability of the seed. If enabled, the receiver verifies the calculated CRC16 for the payload data against the received value in the CRC16 field. The starting value for the CRC16 calculation is configurable, and the CRC16 transmitted may be calculated using either the loaded seed value or a zero seed; the received data CRC16 is checked against both the configured and zero CRC16 seeds. CRC16 detects the following errors: ■ Any one bit in error ■ Any two bits in error (no matter how far apart, which column, and so on) ■ Any odd number of bits in error (no matter where they are) ■ An error burst as wide as the checksum itself Figure 8-1. shows an example packet with SOP, CRC16 and lengths fields enabled. Figure 8-1. Example Default Packet Format 8.4 Packet Buffers and Radio Configuration Registers Packet data and configuration registers are accessed through the SPI interface. All configuration registers are directly addressed through the address field in the SPI packet (as in the CYWUSB6934). Configuration registers are provided to allow configuration of DSSS PN codes, data rate, operating mode, interrupt masks, interrupt status, and others. 8.4.1 Packet Buffers All data transmission and reception use the 16-byte packet buffers: one for transmission and one for reception. The transmit buffer allows a complete packet of up to 16 bytes of payload data to be loaded in one burst SPI transaction, and then transmitted with no further MCU intervention. Similarly, the receive buffer allows an entire packet of payload data up to 16 bytes to be received with no firmware intervention required until packet reception is complete. The CYRF69103 IC supports packet length of up to 40 bytes; interrupts are provided to allow an MCU to use the transmit and receive buffers as FIFOs. When transmitting a packet longer than 16 bytes, the MCU can load 16 bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. Similarly, when receiving packets longer than 16 bytes, the MCU must fetch received data from the FIFO periodically during packet reception to prevent it from overflowing. 8.5 Auto Transaction Sequencer (ATS) The CYRF69103 IC provides automated support for transmission and reception of acknowledged data packets. When transmitting a data packet, the device automatically starts the crystal and synthesizer, enters transmit mode, transmits the packet in the transmit buffer, and then automatically switches to receive mode and waits for a handshake packet—and then automatically reverts to sleep mode or idle mode when either an ACK packet is received, or a time out period expires. Similarly, when receiving in transaction mode, the device waits in receive mode for a valid packet to be received, then automat- ically transitions to transmit mode, transmits an ACK packet, and then switches back to receive mode to await the next packet. The contents of the packet buffers are not affected by the trans- mission or reception of ACK packets. In each case, the entire packet transaction takes place without any need for MCU firmware action; to transmit data the MCU simply needs to load the data packet to be transmitted, set the length, and set the TX GO bit. Similarly, when receiving packets in transaction mode, firmware simply needs to retrieve the fully received packet in response to an interrupt request indicating reception of a packet. P SO P 1 SO P 2 Le ngth CRC 1 6 Pa y loa d D a ta P ream ble n x 16 us 1st F ram in g S y m bol* 2nd F ram in g S y m bol* P a cket length 1 B y te Pe rio d *N ote:32 or 64u s [+] Feedback |
Similar Part No. - CYWUSB6953_10 |
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Similar Description - CYWUSB6953_10 |
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