CY62256VN

Document Number: 001-06512 Rev. *D

Page 8 of 14

Figure 6. Write Cycle No. 2 (CE Controlled)[21, 22, 23]

Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW)[23, 24]

Notes

21. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can

terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

23. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.

25. During this period, the I/Os are in output state and input signals should not be applied.

WE

DATA I/O

ADDRESS

CE

DATA I/O

ADDRESS

NOTE 25

WE

CE

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