16-Mbit (1M x 16) Static RAM

Cypress Semiconductor Corporation

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198 Champion Court

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San Jose

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408-943-2600

Document Number : 38-05328 Rev. *I

Revised November 8, 2010

Features

1M x 16 or as 2M x 8 SRAM

MHz

optimum speed / power

grid array (VFBGA) and 48-pin TSOP I package

Functional Description[1]

The CY62167DV30 is a high-performance CMOS static RAM

organized as 1M words by 16 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life

portable applications such as cellular telephones. The device

also has an automatic power-down feature that significantly

reduces power consumption by 99% when addresses are not

toggling. The device can also be put into standby mode when

Enable and Byte Low Enable are disabled (BHE, BLE HIGH),

LOW).

Writing to the device is accomplished by taking Chip Enables

Reading from the device is accomplished by taking Chip

LOW while forcing the Write Enable (WE) HIGH. If Byte Low

Enable (BLE) is LOW, then data from the memory location

High Enable (BHE) is LOW, then data from memory will appear

sheet for a complete description of Read and Write modes.

Note

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Logic Block Diagram

1M × 16 / 2M x 8

RAM Array

COLUMN DECODER

DATA IN DRIVERS

OE

WE

BLE

BHE

Power-Down

Circuit

BHE

BLE

BYTE