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CY62167DV30LL-55ZXI Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY62167DV30LL-55ZXI Datasheet(HTML) 1 Page - Cypress Semiconductor |
1 / 17 page CY62167DV30 MoBL 16-Mbit (1M x 16) Static RAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number : 38-05328 Rev. *I Revised November 8, 2010 Features ■ Thin small outline package (TSOP I) Configurable as 1M x 16 or as 2M x 8 SRAM ■ Wide voltage range: 2.2 V – 3.6 V ■ Ultra-low active power: Typical active current: 2 mA at f = 1 MHz ■ Ultra-low standby power ■ Easy memory expansion with CE1, CE2 and OE features ■ Automatic power-down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed / power ■ Available in Pb-free and non Pb-free 48-ball very fine ball grid array (VFBGA) and 48-pin TSOP I package Functional Description[1] The CY62167DV30 is a high-performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a Write operation (CE1 LOW, CE2 HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. Note 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Logic Block Diagram 1M × 16 / 2M x 8 RAM Array I/O0–I/O7 A 8 A 7 A 6 A 5 A 2 COLUMN DECODER DATA IN DRIVERS OE A 4 A 3 I/O8–I/O15 WE BLE BHE A 0 A 1 A 9 A10 Power-Down Circuit BHE BLE CE2 CE1 CE2 CE1 BYTE |
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