CY62148DV30

Document Number : 38-05341 Rev. *F

Page 6 of 13

Parameter[9]

Description

55 ns

Unit

Min

Max

Read Cycle

Read cycle time

55

–

ns

Address to data valid

–

55

ns

Data hold from address change

10

–

ns

CE LOW to data valid

–

55

ns

OE LOW to data valid

–

25

ns

OE LOW to Low Z[10]

5

–

ns

OE HIGH to High Z[10,11]

–

20

ns

CE LOW to Low Z[10]

10

–

ns

CE HIGH to High Z[10, 11]

–

20

ns

CE LOW to power-up

0

–

ns

CE HIGH to power-up

–

55

ns

Write Cycle[12]

Write cycle time

55

–

ns

CE LOW to write end

40

–

ns

Address set-up to write end

40

–

ns

Address hold from write end

0

–

ns

Address set-up to write start

0

–

ns

WE pulse width

40

–

ns

Data set-up to write end

25

–

ns

Data hold from write end

0

–

ns

WE LOW to High Z[10, 11]

–

20

ns

WE HIGH to Low Z[10]

10

–

ns

Switching Waveforms

Figure 1. Read Cycle No. 1 (Address Transition Controlled)[13, 14]

ADDRESS

DATA OUT

PREVIOUS DATA VALID

DATA VALID

Notes

terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.

14. WE is HIGH for read cycle.

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