Cypress Semiconductor Corporation

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198 Champion Court

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San Jose

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408-943-2600

Document #: 38-05441 Rev. *H

Revised October 06, 2010

4-Mbit (256K x 16) Static RAM

Features

optimum speed and power

package

Functional Description

The CY62147EV18 is a high performance CMOS static RAM

organized as 256 K words by 16 bits. This device features

advanced circuit design to provide ultra low active current. This

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption when addresses are not toggling. Placing the

device into standby mode reduces power consumption by more

than 99% when deselected (CE HIGH or both BLE and BHE are

in a high impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), both the Byte High

Enable and the Byte Low Enable are disabled (BHE, BLE HIGH),

or during an active write operation (CE LOW and WE LOW).

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW then data

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

Byte High Enable (BHE) is LOW, then data from memory

complete description of read and write modes.

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

256K x 16

RAM Array

COLUMN DECODER

DATA IN DRIVERS

OE

CE

WE

BHE

BLE

BHE

BLE

CE

POWER DOWN

CIRCUIT

Logic Block Diagram

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