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CY62138FV30LL Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY62138FV30LL Datasheet(HTML) 8 Page - Cypress Semiconductor |
8 / 16 page CY62138FV30 MoBL® Document #: 001-08029 Rev. *I Page 8 of 16 Figure 6. Write Cycle No. 2 (CE1 or CE2 controlled) [27, 28, 29, 30] Figure 7. Write Cycle No. 3 (WE controlled, OE LOW) [27, 30] Truth Table CE1 CE2 WE OE Inputs/Outputs Mode Power HX[32] X X High-Z Deselect / Power-down Standby (ISB) X[32] L X X High-Z Deselect/Power-down Standby (ISB) L H H L Data out Read Active (ICC) L H H H High-Z Output disabled Active (ICC) L H L X Data in Write Active (ICC) Notes 27. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 28. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write 29. Data I/O is high impedance if OE = VIH. 30. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains iin high impedance state. 31. During this period, the I/Os are in output state. Do not apply input signals. 32. The ‘X’ (Don’t care) state for the Chip enables (CE1 and CE2) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Switching Waveforms (continued) tWC DATA VALID tAW tSA tPWE tHA tHD tSD tSCE ADDRESS CE DATA I/O WE DATA VALID tHD tSD tLZWE tPWE tSA tHA tAW tSCE tWC tHZWE ADDRESS CE WE DATA I/O NOTE 31 [+] Feedback |
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