FX-730 Low Jitter VCSO Frequency Translator

Vectron International, 267 Lowell Road, Hudson, NH 03051

Tel: 1-88-VECTRON-1

Page 3 of 8

Rev: 18Jun09

Outline Diagram

Suggested Pad Layout

Figure 3.

Figure 4.

Table 2. Pin Out

Pad #

Symbol

I/O

Level

Function

1

BRCLK

I

NC or

LVPECL, LVDS

NC or

For external divider applications = PD Feedback Frequency

2

LD

1

O

CMOS

Lock Detect

Logic “0” = FX Locked

Logic “1” = No input

Output transitioning = Out of Lock

3

GND

GND

Supply

Case and Electrical Ground

4

MODE

2

I

CMOS

FX Operating Mode

Logic “0” = Standard PLL Operation Normal setting

Logic “1” = FIN coupled to FOUT

5

GND

GND

Supply

Case and Electrical Ground

6

LFN

Analog

Loop Filter Node

7

CLFN

Analog

Complementary Loop Filter Node

8

FOUT

O

LVPECL or

LVDS

Frequency Output

9

CFOUT

O

LVPECL or

LVDS

Complementary Frequency Output

10

VCC

I

Supply

Power Supply Voltage (+3.3V ±5%)

11

CFIN

I

LVPECL

Complementary Input Frequency

For CMOS inputs, AC-couple unused input to ground or negative supply.

12

FIN

I

CMOS or

LVPECL

Input Frequency

13

GND

GND

Supply

Case and Electrical Ground

14

CBRCLK

I

NC or

LVPECL, LVDS

NC or

For external divider applications = Comp. PD Feedback Frequency

1.

It is recommended that a buffer driver is used for best noise isolation.

2.

Do not leave the MODE pin floating, it should be set to logic 0 or ground for normal operation.

3.

BRCLK and CBRCLK should be left floating if not used.

4.

FIN, CFIN, BRCLK, and CBRCLK have internal pull-up/pull-down resistors and it is recommended to AC couple these inputs.

mm

[inch]

0.64

[0.025]

3.28

[0.129]

2.54

[0.100]

1.27

[0.050]

0.25

[0.010]

1.02

[0.040]

5.08

[0.200]

1.45

[0.057]

1.02

[0.040]

1.96

[0.077]

1.27

[0.050]

0.20

[0.008]

4.14

[0.163]

2.07

[0.081]

FX730CCCCCC 

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