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DSPIC30F2010 Datasheet(PDF) 8 Page - Microchip Technology |
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DSPIC30F2010 Datasheet(HTML) 8 Page - Microchip Technology |
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8 / 202 page  dsPIC30F2010 DS70118J-page 8 © 2011 Microchip Technology Inc. FIGURE 1-1: dsPIC30F2010 BLOCK DIAGRAM Power-up Timer Oscillator Start-up Timer POR/BOR Reset Watchdog Timer Instruction Decode and Control OSC1/CLKI MCLR AN4/QEA/IC7/CN6/RB4 UART1 SPI1 Motor Control PWM Timing Generation AN5/QEB/IC8/CN7/RB5 16 PCH PCL Program Counter ALU<16> 16 Address Latch Program Memory (12 Kbytes) Data Latch 24 24 24 24 X Data Bus IR I2C™ QEI PCU PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 10-bit ADC Timers PWM3H/RE5 FLTA/INT0/SCK1/OCFA/RE8 Input Capture Module Output Compare Module EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 PORTB PGC/EMUC/U1RX/SDI1/SDA/RF2 PGD/EMUD/U1TX/SDO1/SCL/RF3 PORTF PORTD 16 16 16 16 x 16 W Reg Array Divide Unit Engine DSP Decode ROM Latch 16 Y Data Bus Effective Address X RAGU X WAGU Y AGU EMUD3/AN0/VREF+/CN2/RB0 EMUC3/AN1/VREF-/CN3/RB1 AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 OSC2/CLKO/RC15 16 16 16 16 16 PORTC PORTE 16 16 16 16 8 Interrupt Controller PSV and Table Data Access Control Block Stack Control Logic Loop Control Logic Data Latch Data Latch Y Data (256 bytes) RAM X Data (256 bytes) RAM Address Latch Address Latch Control Signals to Various Blocks EMUC2/OC1/IC1/INT1/RD0 EMUD2/OC2/IC2/INT2/RD1 16 Data EEPROM (1 Kbyte) 16 |
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