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CY2309CSXI-1T Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY2309CSXI-1T
Description  3.3 V Zero Delay Clock Buffer
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2309CSXI-1T Datasheet(HTML) 9 Page - Cypress Semiconductor

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CY2305C
CY2309C
Document Number: 38-07672 Rev. *K
Page 9 of 17
Switching Waveforms
Figure 3. Duty Cycle Timing
Figure 4. All Outputs Rise/Fall Time
Note
12. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Switching characteristics table for CY2305CSXI-1H, CY2305CSXA-1H and CY2309CSXI-1H
Switching characteristics table for CY2305CSXI-1H, CY2305CSXA-1H and CY2309CSXI-1H industrial/automotive-A temperature
device. All parameters are specified with loaded outputs.
Parameter
Name
Description
Min
Typ
Max
Unit
t1
Output frequency
30 pF load
10 pF load
10
10
100
133.33
MHz
MHz
tDC
Output duty cycle[12] = t2  t1 Measured at 1.4 V, Fout > 50 MHz
40
50
60
%
Measured at 1.4 V, Fout <= 50 MHz
45
50
55
%
t3
Rise time[12]
Measured between 0.8 V and 2.0 V
1.5
ns
t4
Fall time[12]
Measured between 0.8 V and 2.0 V
1.5
ns
t5
Output-to-output skew[12]
All outputs equally loaded
200
ps
t6A
Delay, REF rising edge to
CLKOUT rising edge[12]
Measured at VDD/2
0
±350
ps
t6B
Delay, REF rising edge to
CLKOUT rising edge[12]
Measured at VDD/2. Measured in PLL
Bypass mode, CY2309C device only.
15
8.7
ns
t7
Device-to-device skew[12]
Measured at VDD/2 on the CLKOUT pins
of devices
0
700
ps
t8
Output slew rate[12]
Measured between 0.8 V and 2.0 V using
Test circuit #2
1–
V/ns
tJ
Cycle-to-cycle jitter, peak[12] Measured at 66.67 MHz, loaded outputs
175
ps
tLOCK
PLL lock time[12]
Stable power supply, valid clock
presented on REF pin
––
1.0
ms
t1
t2
1.4 V
1.4 V
1.4 V
OUTPUT
t3
3.3 V
0 V
0.8 V
2.0 V
2.0 V
0.8 V
t4
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