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CY3672-USB Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY3672-USB Datasheet(HTML) 10 Page - Cypress Semiconductor |
10 / 14 page CY23FP12-002 Document #: 38-07644 Rev. *B Page 10 of 14 Switching Waveforms Figure 3. Duty Cycle Timing Figure 4. All Outputs Rise/Fall Time Figure 5. Output-Output Skew Figure 6. Input-Output Propagation Delay tTSK Tracking skew Input reference clock at < 50-KHz modulation with ±3.75% spread – – 200 ps tLOCK PLL lock time[5] Stable power supply, valid clock at REF – – 1.0 ms tLD Inserted loop delay Max loop delay for PLL Lock (stable frequency) –– 7 ns Max loop delay to meet Tracking Skew Spec – – 4 ns Switching Characteristics (continued)[5] Parameter Description Test Conditions Min Typ Max Unit [+] Feedback |
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