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CY14B101J2-SXIT Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY14B101J2-SXIT Datasheet(HTML) 9 Page - Cypress Semiconductor |
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9 / 32 page  PRELIMINARY CY14C101J CY14B101J, CY14E101J Document #: 001-54050 Rev. *D Page 9 of 32 ■ ASDISB: Disables nvSRAM AutoStore. The nvSRAM cannot be accessed for tSS time after this instruction has been executed. This setting is not nonvolatile and needs to be followed by a manual STORE sequence if this is desired to survive power cycle. Note If AutoStore is disabled and VCAP is not required, it is required that the VCAP pin is left open. VCAP pin must never be connected to ground. Power-Up RECALL operation cannot be disabled in any case. ■ SLEEP: SLEEP instruction puts the nvSRAM in a sleep mode. When the SLEEP instruction is registered, the nvSRAM performs a STORE operation to secure the data to nonvolatile memory and then enters into sleep mode. Whenever nvSRAM enters into sleep mode, it initiates non volatile STORE cycle which results in losing an endurance cycle per sleep command execution. A STORE cycle starts only if a write to the SRAM has been performed since the last STORE or RECALL cycle. The nvSRAM enters into sleep mode as follows: 1. The Master sends a START command 2. The Master sends Control Registers Slave device ID with I2C Write bit set (R/W = ’0’) 3. The Slave (nvSRAM) sends an ACK back to the Master 4. The Master sends Command Register address (0xAA) 5. The Slave (nvSRAM) sends an ACK back to the Master 6. The Master sends Command Register byte for entering into Sleep mode 7. The Slave (nvSRAM) sends an ACK back to the Master 8. The Master generates a STOP condition. Once in Sleep mode the device starts consuming IZZ current tSLEEP time after SLEEP instruction is registered. The device is not accessible for normal operations until it is out of sleep mode. The nvSRAM wakes up after tWAKE duration after the device slave address is transmitted by the master. Transmitting any of the two slave addresses wakes the nvSRAM from Sleep mode. The nvSRAM device is not accessible during tSLEEP and tWAKE interval, and any attempt to access the nvSRAM device by the master is ignored and nvSRAM sends NACK to the master. As an alternative method of determining when the device is ready, the master can send read or write commands and look for an ACK. Write Protection (WP) The WP pin is an active high pin and protects entire memory and all registers from write operations. To inhibit all the write opera- tions, this pin must be held high. When this pin is high, all memory and register writes are prohibited and address counter is not incremented. This pin is internally pulled LOW and hence can be left open if not used. AutoStore Operation The AutoStore operation is a unique feature of nvSRAM which automatically stores the SRAM data to QuantumTrap cells during power-down. This STORE makes use of an external capacitor (VCAP) and enables the device to safely STORE the data in the nonvolatile memory when power goes down. During normal operation, the device draws current from VCC to charge the capacitor connected to the VCAP pin. When the voltage on the VCC pin drops below VSWITCH during power-down, the device inhibits all memory accesses to nvSRAM and automatically performs a conditional STORE operation using the charge from the VCAP capacitor. The AutoStore operation is not initiated if no write cycle has been performed since the last STORE or RECALL. Note If a capacitor is not connected to VCAP pin, AutoStore must be disabled by issuing the AutoStore Disable instruction specified in “Command Register” on page 8. If AutoStore is enabled without a capacitor on VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the Store. This will corrupt the data stored in nvSRAM Figure 10 shows the proper connection of the storage capacitor (VCAP) for AutoStore operation. Refer to DC Electrical Characteristics on page 19 for the size of the VCAP. Hardware STORE and HSB pin Operation The HSB pin in CY14X101J is used to control and acknowledge STORE operations. If no STORE or RECALL is in progress, this pin can be used to request a Hardware STORE cycle. When the HSB pin is driven LOW, device conditionally initiates a STORE operation after tDELAY duration. An actual STORE cycle starts only if a write to the SRAM has been performed since the last STORE or RECALL cycle. Reads and Writes to the memory are inhibited for tSTORE duration or as long as HSB pin is LOW. The HSB pin also acts as an open drain driver (internal 100 k Ω weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by internal 100 k Ω pull-up resistor. Note For successful last data byte STORE, a hardware STORE should be initiated at least one clock cycle after the last data bit D0 is received. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. Leave the HSB pin unconnected if not used. Figure 10. AutoStore Mode 0.1 uF VCC VCAP VCAP VSS VCC [+] Feedback |
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