 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
CY14B101PA-SF104XIT Datasheet(PDF) 11 Page - Cypress Semiconductor |
|
||||||||||||||||||||||||||||||
CY14B101PA-SF104XIT Datasheet(HTML) 11 Page - Cypress Semiconductor |
|
|
11 / 44 page  PRELIMINARY CY14C101PA CY14B101PA CY14E101PA Document #: 001-54392 Rev. *C Page 11 of 44 Write Protection and Block Protection CY14X101PA provides features for both software and hardware write protection using WRDI instruction and WP. Additionally, this device also provides block protection mechanism through BP0 and BP1 pins of the Status Register. The write enable and disable status of the device is indicated by WEN bit of the Status Register. The write instructions (WRSR, WRITE, and WRTC) and nvSRAM special instruction (STORE, RECALL, ASENB, ASDISB) need the write to be enabled (WEN bit = ‘1’) before they can be issued. Write Enable (WREN) Instruction On power-up, the device is always in the write disable state. The following WRITE, WRSR, WRTC, or nvSRAM special instruction must therefore be preceded by a Write Enable instruction. If the device is not write enabled (WEN = ‘0’), it ignores the write instructions and returns to the standby state when CS is brought HIGH. A new CS falling edge is required to re-initiate serial communication. The instruction is issued following the falling edge of CS. When this instruction is used, the WEN bit of Status Register is set to ‘1’. WEN bit defaults to ‘0’ on power-up. Note After completion of a write instruction (WRSR, WRITE, or WRTC) or nvSRAM special instruction (STORE, RECALL, ASENB, ASDISB) instruction, WEN bit is cleared to ‘0’. This is done to provide protection from any inadvertent writes. Therefore, WREN instruction needs to be used before a new write instruction can be issued Figure 6. Read Status Register (RDSR) Instruction Timing Figure 7. Fast Read Status Register (FAST_RDSR) Instruction Timing Figure 8. Write Status Register (WRSR) Instruction Timing CS SCK SO 0123456 7 SI 0000 0 1 0 0 1 HI-Z 0 12345 6 7 Data LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 Op-Code CS SCK SO 0123456 7 SI 0000 1 0 0 1 HI-Z 8 9 10 11 12 13 14 15 0 Data LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 X X X X X X X X Dummy Byte 0 12345 6 7 Op-Code CS SCK SO 0 1 2 3 4567 SI 0000 0 0 0 1 MSB LSB D2 D3 D7 HI-Z 0 12345 67 Opcode Data in X X X X X [+] Feedback |
Similar Part No. - CY14B101PA-SF104XIT |
|
Similar Description - CY14B101PA-SF104XIT |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
