CY23FP12OXC-002 datasheet(3/14 Pages) CYPRESS

Part #	CY23FP12OXC-002

Description	200-MHz Field Programmable Zero Delay Buffer

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY23FP12-002

Document #: 38-07644 Rev. *B

Page 3 of 14

Pin Configuration

Figure 1. 28-Pin SSOP

Pin Description

Name

I/O

Type

Description

1

REF2

I

LVTTL/LVCMOS

Input reference frequency, 5V-tolerant input.

2

REF1

I

LVTTL/LVCMOS

Input reference frequency, 5V-tolerant input.

3

CLKB0

O

LVTTL

Clock output, Bank B.

4

CLKB1

O

LVTTL

Clock output, Bank B.

5VSSB

PWR

POWER

Ground for Bank B.

6

CLKB2

O

LVTTL

Clock output, Bank B.

7

CLKB3

O

LVTTL

Clock output, Bank B.

8VDDB

PWR

POWER

2.5-V or 3.3-V supply, Bank B.

9VSSB

PWR

POWER

Ground for Bank B.

10

CLKB4

O

LVTTL

Clock output, Bank B.

11

CLKB5

O

LVTTL

Clock output, Bank B.

12

VDDB

PWR

POWER

2.5-V or 3.3-V supply, Bank B.

13

VDDC

PWR

POWER

3.3 V core supply.

14

S2

I

LVTTL

Select input.

15

S1

I

LVTTL

Select input.

16

VSSC

PWR

POWER

Ground for core.

17

VDDA

PWR

POWER

2.5-V or 3.3-V supply, Bank A.

18

CLKA5

O

LVTTL

Clock output, Bank A.

19

CLKA4

O

LVTTL

Clock output, Bank A.

20

VSSA

PWR

POWER

Ground for Bank A.

21

VDDA

PWR

POWER

2.5-V or 3.3-V supply Bank A.

22

CLKA3

O

LVTTL

Clock output, Bank A.

23

CLKA2

O

LVTTL

Clock output, Bank A.

24

VSSA

PWR

POWER

Ground for Bank A.

25

CLKA1

O

LVTTL

Clock output, Bank A.

26

CLKA0

O

LVTTL

CLock output, Bank A.

27

FBK

I

LVTTL

PLL feedback input.

28

REFSEL

I

LVTTL

Reference select input. When REFSEL = 0, REF1 is

selected. When REFSEL = 1, REF2 is selected.

21

28

REFSEL

FBK

CLKA0

CLKA1

VSSA

CLKA2

CLKA3

VDDA

1

2

3

4

5

6

7

8

22

23

24

25

26

27

REF2

REF1

CLKB0

CLKB1

VSSB

CLKB2

CLKB3

VDDB

17

VDDA

20

VSSA

19

CLKA4

18

CLKA5

16

VSSC

15

S1

9

VSSB

12

VDDB

13

VDDC

10

CLKB4

11

CLKB5

14

S2

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