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CY23FP12OXI Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY23FP12OXI
Description  200 MHz Field Programmable Zero Delay Buffer
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY23FP12OXI Datasheet(HTML) 5 Page - Cypress Semiconductor

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CY23FP12
Document #: 38-07246 Rev. *G
Page 5 of 15
Table 2 lists independent functions that can be assigned to each of the four S1 and S2 combinations. When a particular S1 and S2
combination is selected, the device assumes the configuration (which is essentially a set of functions given in Table 2) that has been
preassigned to that particular combination.
Pull-down Enable
Enables/Disables internal pulldowns on all outputs
Enable
Fbk Pull-down Enable
Enables/Disables internal pulldowns on the feedback path (applicable to both internal and
external feedback topologies)
Enable
Fbk Sel
Selects between the internal and the external feedback topologies
External
Table 2. Programmable Functions for S1/S2 Combinations
Function
Description
Default
Output Enable CLKB[5:4] Enables/Disables CLKB[5:4] output pair
See Table 4 on
page 6
Output Enable CLKB[3:2] Enables/Disables CLKB[3:2] output pair
See Table 4 on
page 6
Output Enable CLKB[1:0] Enables/Disables CLKB[1:0] output pair
See Table 4 on
page 6
Output Enable CLKA[5:4] Enables/Disables CLKA[5:4] output pair
See Table 4 on
page 6
Output Enable CLKA[3:2] Enables/Disables CLKA[3:2] output pair
See Table 4 on
page 6
Output Enable CLKA[1:0] Enables/Disables CLKA[1:0] output pair
See Table 4 on
page 6
Auto Power-down Enable Enables/Disables the auto power down circuit, which monitors the reference clock rising
edges and shuts down the device in case of a reference “failure.” This failure is triggered
by a drift in reference frequency below a set limit. This auto power down circuit is disabled
internally when one or more of the outputs are configured to be driven directly from the
reference clock.
Enable
PLL Power-down
Shuts down the PLL when the device is configured as a non-PLL fanout buffer.
PLL Enabled
M[7:0]
Assigns an eight-bit value to reference divider –M. The divider can be any integer value
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
2
N[7:0]
Assigns an eight-bit value to feedback divider –N. The divider can be any integer value
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
2
X[6:0]
Assigns a seven-bit value to output divider –X. The divider can be any integer value from
5 to 130. Divide by 1,2,3, and 4 are preprogrammed on the device and can be activated
by the appropriate output mux setting.
1
Divider Source
Selects between the PLL output and the reference clock as the source clock for the output
dividers.
See Table 4 on
page 6
CLKA54 Source
Independently selects one out of the eight possible output dividers that will connect to the
CLKA5 and CLKA4 pair. Please refer to Table 3 on page 6 for a list of divider values.
Divide by 2
CLKA32 Source
Independently selects one out of the eight possible output dividers that will connect to the
CLKA3 and CLKA2 pair. Please refer to Table 3 on page 6 for a list of divider values.
Divide by 2
CLKA10 Source
Independently selects one out of the eight possible output dividers that will connect to the
CLKA1 and CLKA0 pair. Please refer to Table 3 on page 6 for a list of divider values.
Divide by 2
CLKB54 Source
Independently selects one out of the eight possible output dividers that will connect to the
CLKB5 and CLKB4 pair. Please refer to Table 3 on page 6 for a list of divider values.
Divide by 2
CLKB32 Source
Independently selects one out of the eight possible output dividers that will connect to the
CLKB3 and CLKB2 pair. Please refer to Table 3 on page 6 for a list of divider values.
Divide by 2
CLKB10 Source
Independently selects one out of the eight possible output dividers that will connect to the
CLKB1 and CLKB0 pair. Please refer to Table 3 on page 6 for a list of divider values.
Divide by 2
Table 1. Programmable Functions
Configuration
Description
Default
[+] Feedback


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