CY23FP12-002

Document #: 38-07644 Rev. *B

Page 6 of 14

Table 3 is a list of output dividers that are independently selected to connect to each output pair.

In the default (pre-programmed) state of the device, S1 and S2 pins will function as indicated in Table 4. The CY23FP12-002 can be

programmed to other configurations.

Table 3. Output Dividers

CLKA/B Source

Output Connects To

0 [000]

REF

1 [001]

Divide by 1

2 [010]

Divide by 2

3 [011]

Divide by 3

4 [100]

Divide by 4

5 [101]

Divide by X

6 [110]

Divide by 2X[1]

7 [111]

TEST mode [LOCK signal][2]

Table 4. Pre-Programmed Configuration

Outputs

S2, S1 DivSrc

Example Output

REF Input (MHz) VCO (MHz)

Output (MHz)

ClkA0, A1

00

1

25

200

200

ClkA2, A3

00

3

25

200

66.7

ClkA4, A5

00

X=6

25

200

33.3

ClkB0, B1

00

X=6

25

200

33.3

ClkB2, B3

00

4

25

200

50

ClkB4, B5

00

Ref

25

200

25

ClkA0, A1

01

4

100

200

50

ClkA2, A3

01

4

100

200

50

ClkA4, A5

01

4

100

200

50

ClkB0, B1

01

4

100

200

50

ClkB2, B3

01

X=8

100

200

25

ClkB4, B5

01

X=8

100

200

25

ClkA0, A1

10

X=8

33.3

266.6

33.3

ClkA2, A3

10

X=8

33.3

266.6

33.3

ClkA4, A5

10

X=8

33.3

266.6

33.3

ClkB0, B1

10

4

33.3

266.6

66.6

ClkB2, B3

10

4

33.3

266.6

66.6

ClkB4, B5

10

4

33.3

266.6

66.6

ClkA0, A1

11

Ref

100

powerdown

100

ClkA2, A3

11

Ref

100

powerdown

100

ClkA4, A5

11

Ref

100

powerdown

100

ClkB0, B1

11

2

100

powerdown

50

ClkB2, B3

11

2

100

powerdown

50

ClkB4, B5

11

2

100

powerdown

50

Notes

1. Outputs will be rising edge aligned only to those outputs using this same device setting.

2. When the source of an output pair is set to [111], the output pair becomes lock indicator signal. For example, if the source of an output pair (CLKA0, CLKA1) is set

to [111], the CLKA0 and CLKA1, becomes lock indicator signals. In non-invert mode, CLKA0 and CLKA1 signals will be high when the PLL is in lock mode. If

CLKA0 is in an invert mode, the CLKA0 will be low and the CLKA1 will be high when the PLL is in lock mode.

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