CY23FP12

Document #: 38-07246 Rev. *G

Page 4 of 15

Figure 2. Basic PLL Block Diagram

The following table lists independent functions that can be programmed with a volume or prototype programmer on the “default” silicon.

Table 1. Programmable Functions

Configuration

Description

Default

DC Drive Bank A

Programs the drive strength of Bank A outputs. The user can select one out of two possible

drive strength settings that produce output DC currents in the range of ±16 mA to ±20 mA.

+16 mA

DC Drive Bank B

Programs the drive strength of Bank B outputs. The user can select one out of two possible

drive strength settings that produce output DC currents in the range of ±16 mA to ±20 mA.

+16 mA

Output Enable for Bank B

clocks

Enables/Disables CLKB[5:0] outputs. Each of the six outputs can be disabled individually

if not used, to minimize electromagnetic interference (EMI) and switching noise.

Enable

Output Enable for Bank A

clocks

Enables/Disables CLKA[5:0] outputs. Each of the six outputs can be disabled individually

if not used, to minimize EMI and switching noise.

Enable

Inv CLKA0

Generates an inverted clock on the CLKA0 output. When this option is programmed,

CLKA0 and CLKA1 will become complimentary pairs.

Non-invert

Inv CLKA2

Generates an inverted clock on the CLKA2 output. When this option is programmed,

CLKA2 and CLKA3 will become complimentary pairs.

Non-invert

Inv CLKA4

Generates an inverted clock on the CLKA4 output. When this option is programmed,

CLKA4 and CLKA5 will become complimentary pairs.

Non-invert

Inv CLKB0

Generates an inverted clock on the CLKB0 output. When this option is programmed,

CLKB0 and CLKB1 will become complimentary pairs.

Non-invert

Inv CLKB2

Generates an inverted clock on the CLKB2 output. When this option is programmed,

CLKB2 and CLKB3 will become complimentary pairs.

Non-invert

Inv CLKB4

Generates an inverted clock on the CLKB4 output. When this option is programmed,

CLKB4 and CLKB5 will become complimentary pairs.

Non-invert

/1,/2,/3,/4,

/x,/2x

/1,/2,/3,/4,

/x,/2x

/1,/2,/3,/4,

/x,/2x

/1,/2,/3,/4,

/x,/2x

/1,/2,/3,/4,

/x,/2x

/1,/2,/3,/4,

/x,/2x

PLL

/M

/N

Output

Function

Select

Matrix

REF

FBK

CLKB5

CLKB4

CLKB3

CLKB2

CLKB1

CLKB0

CLKA5

CLKA4

CLKA3

CLKA2

CLKA1

CLKA0

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