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CY8C27243-24PVXIT Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY8C27243-24PVXIT
Description  PSoC짰 Programmable System-on-Chip?
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C27243-24PVXIT Datasheet(HTML) 4 Page - Cypress Semiconductor

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CY8C27143, CY8C27243
CY8C27443, CY8C27543
CY8C27643
Document Number: 38-12012 Rev. *T
Page 4 of 63
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also enable signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This lets you the optimum
choice of system resources for your application. Family
resources are shown in the table titled PSoC Device
Characteristics on page 5.
Analog System
The analog system is composed of 12 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are as follows:
ADCs (up to 4, with 6- to 14-bit resolution, selectable as
incremental, delta sigma, and SAR)
Filters (2, 4, 6, and 8 pole band pass, low pass, and notch)
Amplifiers (up to four, with selectable gain to 48x)
Instrumentation amplifiers (up to two, with selectable gain to
93x)
Comparators (up to four, with 16 selectable thresholds)
DACs (up to four, with 6- to 9-bit resolution)
Multiplying DACs (up to four, with 6- to 9-bit resolution)
High current output drivers (four with 30 mA drive as a core
resource)
1.3-V reference (as a system resource)
DTMF dialer
Modulators
Correlators
Peak detectors
Many other topologies possible
Analog blocks are provided in columns of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks, as shown in the following figure.
Figure 2. Analog System Block Diagram
ACB00
ACB01
Block Array
Array Input Configuration
ACI1[1:0]
ACI2[1:0]
ACB02
ACB03
ASC12
ASD13
ASD22
ASC23
ASD20
ACI0[1:0]
ACI3[1:0]
P0[6]
P0[4]
P0[2]
P0[0]
P2[2]
P2[0]
P2[6]
P2[4]
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Reference
Generators
AGNDIn
RefIn
Bandgap
RefHi
RefLo
AGND
ASD11
ASC21
ASC10
Interface to
Digital System
M8C Interface (Address Bus, Data Bus, Etc.)
Analog Reference
[+] Feedback


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