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CY8C9520A Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY8C9520A Datasheet(HTML) 11 Page - Cypress Semiconductor |
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11 / 32 page  CY8C9520A CY8C9540A, CY8C9560A Document Number: 38-12036 Rev. *E Page 11 of 32 Register Mapping Table The register address is auto-incrementing. If the master device writes or reads data to or from one register and then continues data transfer in the same I2C transaction, sequential bytes are written or read to or from the following registers. For example, if the first byte is sent to the Output Port 1 register, then the next bytes are written to Output Port 2, Output Port 3, Output Port 4 etc. The first byte of each write transaction is treated as the register address. To read data from a seires of registers, the master device must write the starting register address byte then perform a start and series of read transactions. If no address was sent, reads start from address 0. To read a specific register address, the master device must write the register address byte, then perform a start and read trans- action. See Figure 7 on page 10. The device’s register mapping is listed in Table 7. Register Descriptions The registers for the CY8C95xx are described in the sections that follow. Note that the PWM registers are located at addresses 28h to 2Bh. Input Port Registers (00h - 07h) These registers represent actual logical levels on the pins and are used for I/O port reading operations. They are read only. The Inversion registers changes the state of reads to these ports. Output Port Registers (08h - 0Fh) These registers are used for writing data to GPIO ports. By default, all ports are in the pull up mode allowing quasi-bidirec- tional I/O. To allow input operations without reconfiguration, these registers have to store ’1’s. Output register data also affects pin states when PWMs are enabled. See Table 8 on page 12 for details. See Figure 7 on page 10 illustrates port read/write procedures. The Inversion registers have no effect on these ports. Table 7. The Device Register Address Map Address Register Default Register Value 00h Input Port 0 None 01h Input Port 1 None 02h Input Port 2 None 03h Input Port 3 None 04h Input Port 4 None 05h Input Port 5 None 06h Input Port 6 None 07h Input Port 7 None 08h Output Port 0 FFh 09h Output Port 1 FFh 0Ah Output Port 2 FFh 0Bh Output Port 3 FFh 0Ch Output Port 4 FFh 0Dh Output Port 5 FFh 0Eh Output Port 6 FFh 0Fh Output Port 7 FFh 10h Interrupt Status Port 0 00h 11h Interrupt Status Port 1 00h 12h Interrupt Status Port 2 00h 13h Interrupt Status Port 3 00h 14h Interrupt Status Port 4 00h 15h Interrupt Status Port 5 00h 16h Interrupt Status Port 6 00h 17h Interrupt Status Port 7 00h 18h Port Select 00h 19h Interrupt Mask FFh 1Ah Select PWM for Port Output 00h 1Bh Inversion 00h 1Ch Pin Direction - Input/Output 00h 1Dh Drive Mode - Pull Up FFh 1Eh Drive Mode - Pull Down 00h 1Fh Drive Mode - Open Drain High 00h 20h Drive Mode - Open Drain Low 00h 21h Drive Mode - Strong 00h 22h Drive Mode - Slow Strong 00h 23h Drive Mode - High-Z 00h 24h Reserved None 25h Reserved None 26h Reserved None 27h Reserved None 28h PWM Select 00h 29h Config PWM 00h 2Ah Period PWM FFh 2Bh Pulse Width PWM 80h 2Ch Programmable Divider FFh 2Dh Enable WDE, EEE, EERO 00h 2Eh Device ID/Status 20h/40h/60h 2Fh Watchdog 00h 30h Command 00h Table 7. The Device Register Address Map (continued) Address Register Default Register Value [+] Feedback |
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