CY7C12481KV18-400BZC datasheet(10/29 Pages) CYPRESS

Part #	CY7C12481KV18-400BZC

Description	36-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY7C12461KV18, CY7C12571KV18

CY7C12481KV18, CY7C12501KV18

Document Number: 001-53194 Rev. *I

Page 10 of 29

Valid Data Indicator (QVLD)

QVLD is provided on the DDR II+ to simplify data capture on high

speed systems. The QVLD is generated by the DDR II+ device

along with data output. This signal is also edge aligned with the

echo clock and follows the timing of any data pin. This signal is

asserted half a cycle before valid data arrives.

PLL

These chips use a PLL that is designed to function between 120

MHz and the specified maximum clock frequency. During power

up, when the DOFF is tied HIGH, the PLL is locked after 20

s

of stable clock. The PLL can also be reset by slowing or stopping

the input clock K and K for a minimum of 30 ns. However, it is not

necessary to reset the PLL to lock to the desired frequency. The

PLL automatically locks 20

s after a stable clock is presented.

The PLL may be disabled by applying ground to the DOFF pin.

When the PLL is turned off, the device behaves in DDR I mode

(with one cycle latency and a longer access time). For infor-

mation, refer to the application note, PLL Considerations in

QDRII/DDRII/QDRII+/DDRII+.

Application Example

Figure 1 shows two DDR II+ used in an application.

Figure 1. Application Example

DQ

A

SRAM#2

LD

CQ/CQ

K

ZQ

K

R/W BWS

BUS

MASTER

(CPU or ASIC)

DQ

Addresses

LD

R/W

R = 250ohms

Source CLK

Echo Clock1/Echo Clock1

Echo Clock2/Echo Clock2

R = 250ohms

BWS

DQ

A

SRAM#1

LD

K

ZQ

CQ/CQ

K

R/W BWS

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