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CY7C11461KV18 Datasheet(PDF) 24 Page - Cypress Semiconductor

Part No. CY7C11461KV18
Description  18-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C11461KV18 Datasheet(HTML) 24 Page - Cypress Semiconductor

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CY7C11461KV18, CY7C11571KV18
CY7C11481KV18, CY7C11501KV18
Document Number: 001-53198 Rev. *F
Page 24 of 29
Switching Characteristics
Over the Operating Range[21, 22]
Cypress
Parameter
Consortium
Parameter
Description
450 MHz
400 MHz
375 MHz
333 MHz
Unit
Min Max Min Max Min Max Min Max
tPOWER
VDD(Typical) to the First Access[23]
1–
1–1
–1–
ms
tCYC
tKHKH
K Clock Cycle Time
2.20 8.4 2.50
8.4 2.66 8.4
3.0
8.4
ns
tKH
tKHKL
Input Clock (K/K) HIGH
0.4
0.4
0.4
0.4
ns
tKL
tKLKH
Input Clock (K/K) LOW
0.4
0.4
0.4
0.4
ns
tKHKH
tKHKH
K Clock Rise to K Clock Rise
(rising edge to rising edge)
0.94
1.06
1.13
1.28
ns
Setup Times
tSA
tAVKH
Address Setup to K Clock Rise
0.275
0.4
0.4
0.4
ns
tSC
tIVKH
Control Setup to K Clock Rise (LD, R/W)
0.275
0.4
0.4
0.4
ns
tSCDDR
tIVKH
Double Data Rate Control Setup to Clock (K/K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.22
0.28
0.28
0.28
ns
tSD
tDVKH
D[X:0] Setup to Clock (K/K) Rise
0.22–
0.28–0.28
0.28
ns
Hold Times
tHA
tKHAX
Address Hold after K Clock Rise
0.275
0.4
0.4
0.4
ns
tHC
tKHIX
Control Hold after K Clock Rise (LD, R/W)
0.275
0.4
0.4
0.4
ns
tHCDDR
tKHIX
Double Data Rate Control Hold after Clock (K/K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.22
0.28
0.28
0.28
ns
tHD
tKHDX
D[X:0] Hold after Clock (K/K) Rise
0.22–
0.28–0.28
0.28
ns
Output Times
tCO
tCHQV
K/K Clock Rise to Data Valid
0.45
–0.45–
0.45
–0.45
ns
tDOH
tCHQX
Data Output Hold after Output K/K Clock Rise
(Active to Active)
–0.45
–0.45
–0.45
–0.45
ns
tCCQO
tCHCQV
K/K Clock Rise to Echo Clock Valid
0.45
0.45
0.45
0.45
ns
tCQOH
tCHCQX
Echo Clock Hold after K/K Clock Rise
–0.45
–0.45
–0.45
–0.45
ns
tCQD
tCQHQV
Echo Clock High to Data Valid
0.15
0.20
0.20
0.20
ns
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
–0.15
–0.20
–0.20
–0.20
ns
tCQH
tCQHCQL
Output Clock (CQ/CQ) HIGH[24]
0.85
1.00
1.08
1.25
ns
tCQHCQH tCQHCQH
CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge)[24]
0.85
1.00
1.08
1.25
ns
tCHZ
tCHQZ
Clock (K/K) Rise to High Z
(Active to High Z) [25, 26]
0.45
0.45
0.45
0.45
ns
tCLZ
tCHQX1
Clock (K/K) Rise to Low Z[25, 26]
–0.45
–0.45
–0.45
–0.45
ns
tQVLD
tCQHQVLD
Echo Clock High to QVLD Valid[27]
–0.15 0.15 –0.20 0.20 –0.20 0.20 –0.20 0.20
ns
PLL Timing
tKC Var
tKC Var
Clock Phase Jitter
0.15
0.20
0.20
0.20
ns
tKC lock
tKC lock
PLL Lock Time (K)
20–20–20–
20
s
tKC Reset
tKC Reset
K Static to PLL Reset[28]
30–30–30–
30
ns
Notes
22. When a part with a maximum frequency above 333 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
23. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD min initially before a read or write operation can be initiated.
24. These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production.
25. tCHZ, tCLZ are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured 100 mV from steady-state voltage.
26. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
27. tQVLD specification is applicable for both rising and falling edges of QVLD signal.
28. Hold to >VIH or <VIL.
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