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CY7C11461KV18 Datasheet(PDF) 22 Page - Cypress Semiconductor

Part No. CY7C11461KV18
Description  18-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Download  29 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C11461KV18 Datasheet(HTML) 22 Page - Cypress Semiconductor

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CY7C11461KV18, CY7C11571KV18
CY7C11481KV18, CY7C11501KV18
Document Number: 001-53198 Rev. *F
Page 22 of 29
IDD [20]
VDD Operating Supply
VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
450 MHz
(x8)
630
mA
(x9)
630
(x18)
650
(x36)
820
400 MHz
(x8)
580
mA
(x9)
580
(x18)
590
(x36)
750
375 MHz
(x8)
550
mA
(x9)
550
(x18)
570
(x36)
710
333 MHz
(x8)
510
mA
(x9)
510
(x18)
520
(x36)
640
ISB1
Automatic Power Down
Current
Max VDD,
Both Ports Deselected,
VIN  VIH or VIN  VIL
f = fMAX = 1/tCYC,
Inputs Static
450 MHz
(x8)
340
mA
(x9)
340
(x18)
340
(x36)
340
400 MHz
(x8)
320
mA
(x9)
320
(x18)
320
(x36)
320
375 MHz
(x8)
310
mA
(x9)
310
(x18)
310
(x36)
310
333 MHz
(x8)
290
mA
(x9)
290
(x18)
290
(x36)
290
AC Electrical Characteristics
Over the Operating Range[12]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VIH
Input HIGH Voltage
VREF + 0.2
VDDQ + 0.24
V
VIL
Input LOW Voltage
–0.24
VREF – 0.2
V
DC Electrical Characteristics (continued)
Over the Operating Range[13]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
Note
20. The operation current is calculated with 50% read cycle and 50% write cycle.
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