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CY7C11461KV18 Datasheet(PDF) 20 Page - Cypress Semiconductor

Part No. CY7C11461KV18
Description  18-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C11461KV18 Datasheet(HTML) 20 Page - Cypress Semiconductor

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CY7C11461KV18, CY7C11571KV18
CY7C11481KV18, CY7C11501KV18
Document Number: 001-53198 Rev. *F
Page 20 of 29
Power Up Sequence in DDR II+ SRAM
DDR II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power Up Sequence
Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
Apply VDD before VDDQ.
Apply VDDQ before VREF or at the same time as VREF.
Drive DOFF HIGH.
Provide stable DOFF (HIGH), power and clock (K, K) for 20 s
to lock the PLL.
PLL Constraints
PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
The PLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20
s of stable clock to
relock to the desired clock frequency.
Figure 5. Power Up Waveforms
> 20 s Stable clock
Start Normal
Operation
DOFF
Stable (< +/- 0.1V DC per 50ns )
Fix HIGH (or tie to VDDQ)
K
K
DDQ
DD
V
V
/
DDQ
DD
V
V
/
Clock Start (Clock Starts after
Stable)
DDQ
DD
V
V
/
Unstable Clock
[+] Feedback


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