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CY7C11461KV18 Datasheet(PDF) 2 Page - Cypress Semiconductor

Part No. CY7C11461KV18
Description  18-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Download  29 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C11461KV18 Datasheet(HTML) 2 Page - Cypress Semiconductor

 
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CY7C11461KV18, CY7C11571KV18
CY7C11481KV18, CY7C11501KV18
Document Number: 001-53198 Rev. *F
Page 2 of 29
Note
1. The Cypress QDR-II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD.
Logic Block Diagram (CY7C11461KV18)
Logic Block Diagram (CY7C11571KV18)
Write
Reg
Write
Reg
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
8
16
8
NWS[1:0]
VREF
8
20
8
LD
Control
R/W
DOFF
8
DQ[7:0]
8
CQ
CQ
QVLD
Write
Reg
Write
Reg
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
9
18
9
BWS[0]
VREF
9
20
9
LD
Control
R/W
DOFF
9
DQ[8:0]
9
CQ
CQ
QVLD
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