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CY7C11461KV18 Datasheet(PDF) 16 Page - Cypress Semiconductor

Part No. CY7C11461KV18
Description  18-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Download  29 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C11461KV18 Datasheet(HTML) 16 Page - Cypress Semiconductor

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CY7C11461KV18, CY7C11571KV18
CY7C11481KV18, CY7C11501KV18
Document Number: 001-53198 Rev. *F
Page 16 of 29
Figure 3. TAP Controller Block Diagram
TAP Electrical Characteristics
Over the Operating Range[11, 12, 13]
Parameter
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH Voltage
IOH =2.0 mA
1.4
V
VOH2
Output HIGH Voltage
IOH =100 A1.6
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 A0.2
V
VIH
Input HIGH Voltage
0.65VDD VDD + 0.3
V
VIL
Input LOW Voltage
–0.3
0.35VDD
V
IX
Input and Output Load Current
GND
 VI  VDD
–5
5
A
0
0
1
2
.
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
.
.
.
108
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
Notes
11. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the DC Electrical Characteristics Table.
12. Overshoot: VIH(AC) < VDDQ + 0.3V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3V (Pulse width less than tCYC/2).
13. All Voltage referenced to Ground.
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